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19 lines
311 B
Verilog
19 lines
311 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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bar
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);
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wire foo;
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output bar;
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// Oh dear.
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assign foo = bar;
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assign bar = foo;
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endmodule
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