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8 lines
483 KiB
Plaintext
8 lines
483 KiB
Plaintext
{
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"version": 3,
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"sources": ["../src/common/cpu/disasm6502.ts", "../src/common/cpu/ZilogZ80.ts", "../src/common/audio.ts", "../src/common/probe.ts", "../src/common/devices.ts", "../src/common/cpu/disasmz80.ts", "../src/common/wasmplatform.ts", "../src/common/cpu/6809.ts", "../src/common/cpu/MOS6502.ts", "../src/common/baseplatform.ts"],
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"sourcesContent": ["\nimport { hex } from \"../util\";\n\nexport var OPS_6502 = [\n {mn:\"BRK\",am:\"\",nb:1,il:0,c1:7,c2:0}, // 00\n {mn:\"ORA\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // 01\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 02\n {mn:\"SLO\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // 03\n {mn:\"NOP\",am:\"aa\",nb:2,il:1,c1:3,c2:0}, // 04\n {mn:\"ORA\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 05\n {mn:\"ASL\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // 06\n {mn:\"SLO\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // 07\n {mn:\"PHP\",am:\"\",nb:1,il:0,c1:3,c2:0}, // 08\n {mn:\"ORA\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // 09\n {mn:\"ASL\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 0A\n {mn:\"ANC\",am:\"#aa\",nb:2,il:1,c1:2,c2:0}, // 0B\n {mn:\"NOP\",am:\"AAAA\",nb:3,il:1,c1:4,c2:0}, // 0C\n {mn:\"ORA\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 0D\n {mn:\"ASL\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // 0E\n {mn:\"SLO\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // 0F\n {mn:\"BPL\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // 10\n {mn:\"ORA\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // 11\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 12\n {mn:\"SLO\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // 13\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // 14\n {mn:\"ORA\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 15\n {mn:\"ASL\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // 16\n {mn:\"SLO\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // 17\n {mn:\"CLC\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 18\n {mn:\"ORA\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // 19\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 1A\n {mn:\"SLO\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // 1B\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // 1C\n {mn:\"ORA\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // 1D\n {mn:\"ASL\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // 1E\n {mn:\"SLO\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // 1F\n {mn:\"JSR\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // 20\n {mn:\"AND\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // 21\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 22\n {mn:\"RLA\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // 23\n {mn:\"BIT\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 24\n {mn:\"AND\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 25\n {mn:\"ROL\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // 26\n {mn:\"RLA\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // 27\n {mn:\"PLP\",am:\"\",nb:1,il:0,c1:4,c2:0}, // 28\n {mn:\"AND\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // 29\n {mn:\"ROL\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 2A\n {mn:\"ANC\",am:\"#aa\",nb:2,il:1,c1:2,c2:0}, // 2B\n {mn:\"BIT\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 2C\n {mn:\"AND\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 2D\n {mn:\"ROL\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // 2E\n {mn:\"RLA\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // 2F\n {mn:\"BMI\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // 30\n {mn:\"AND\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // 31\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 32\n {mn:\"RLA\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // 33\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // 34\n {mn:\"AND\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 35\n {mn:\"ROL\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // 36\n {mn:\"RLA\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // 37\n {mn:\"SEC\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 38\n {mn:\"AND\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // 39\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 3A\n {mn:\"RLA\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // 3B\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // 3C\n {mn:\"AND\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // 3D\n {mn:\"ROL\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // 3E\n {mn:\"RLA\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // 3F\n {mn:\"RTI\",am:\"\",nb:1,il:0,c1:6,c2:0}, // 40\n {mn:\"EOR\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // 41\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 42\n {mn:\"SRE\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // 43\n {mn:\"NOP\",am:\"aa\",nb:2,il:1,c1:3,c2:0}, // 44\n {mn:\"EOR\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 45\n {mn:\"LSR\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // 46\n {mn:\"SRE\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // 47\n {mn:\"PHA\",am:\"\",nb:1,il:0,c1:3,c2:0}, // 48\n {mn:\"EOR\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // 49\n {mn:\"LSR\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 4A\n {mn:\"ASR\",am:\"#aa\",nb:2,il:1,c1:2,c2:0}, // 4B\n {mn:\"JMP\",am:\"AAAA\",nb:3,il:0,c1:3,c2:0}, // 4C\n {mn:\"EOR\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 4D\n {mn:\"LSR\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // 4E\n {mn:\"SRE\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // 4F\n {mn:\"BVC\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // 50\n {mn:\"EOR\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // 51\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 52\n {mn:\"SRE\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // 53\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // 54\n {mn:\"EOR\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 55\n {mn:\"LSR\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // 56\n {mn:\"SRE\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // 57\n {mn:\"CLI\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 58\n {mn:\"EOR\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // 59\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 5A\n {mn:\"SRE\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // 5B\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // 5C\n {mn:\"EOR\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // 5D\n {mn:\"LSR\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // 5E\n {mn:\"SRE\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // 5F\n {mn:\"RTS\",am:\"\",nb:1,il:0,c1:6,c2:0}, // 60\n {mn:\"ADC\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // 61\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 62\n {mn:\"RRA\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // 63\n {mn:\"NOP\",am:\"aa\",nb:2,il:1,c1:3,c2:0}, // 64\n {mn:\"ADC\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 65\n {mn:\"ROR\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // 66\n {mn:\"RRA\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // 67\n {mn:\"PLA\",am:\"\",nb:1,il:0,c1:4,c2:0}, // 68\n {mn:\"ADC\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // 69\n {mn:\"ROR\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 6A\n {mn:\"ARR\",am:\"#aa\",nb:2,il:1,c1:2,c2:0}, // 6B\n {mn:\"JMP\",am:\"(AAAA)\",nb:3,il:0,c1:5,c2:0}, // 6C\n {mn:\"ADC\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 6D\n {mn:\"ROR\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // 6E\n {mn:\"RRA\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // 6F\n {mn:\"BVS\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // 70\n {mn:\"ADC\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // 71\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 72\n {mn:\"RRA\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // 73\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // 74\n {mn:\"ADC\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 75\n {mn:\"ROR\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // 76\n {mn:\"RRA\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // 77\n {mn:\"SEI\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 78\n {mn:\"ADC\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // 79\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 7A\n {mn:\"RRA\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // 7B\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // 7C\n {mn:\"ADC\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // 7D\n {mn:\"ROR\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // 7E\n {mn:\"RRA\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // 7F\n {mn:\"NOP\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // 80\n {mn:\"STA\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // 81\n {mn:\"NOP\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // 82\n {mn:\"SAX\",am:\"(aa,x)\",nb:2,il:1,c1:6,c2:1}, // 83\n {mn:\"STY\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 84\n {mn:\"STA\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 85\n {mn:\"STX\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // 86\n {mn:\"SAX\",am:\"aa\",nb:2,il:1,c1:3,c2:0}, // 87\n {mn:\"DEY\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 88\n {mn:\"NOP\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // 89\n {mn:\"TXA\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 8A\n {mn:\"ANE\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // 8B\n {mn:\"STY\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 8C\n {mn:\"STA\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 8D\n {mn:\"STX\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // 8E\n {mn:\"SAX\",am:\"AAAA\",nb:3,il:1,c1:4,c2:0}, // 8F\n {mn:\"BCC\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // 90\n {mn:\"STA\",am:\"(aa),y\",nb:2,il:0,c1:6,c2:0}, // 91\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // 92\n {mn:\"SHA\",am:\"(aa),y\",nb:2,il:1,c1:0,c2:0}, // 93\n {mn:\"STY\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 94\n {mn:\"STA\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // 95\n {mn:\"STX\",am:\"aa,y\",nb:2,il:0,c1:4,c2:0}, // 96\n {mn:\"SAX\",am:\"aa,y\",nb:3,il:1,c1:4,c2:1}, // 97\n {mn:\"TYA\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 98\n {mn:\"STA\",am:\"AAAA,y\",nb:3,il:0,c1:5,c2:0}, // 99\n {mn:\"TXS\",am:\"\",nb:1,il:0,c1:2,c2:0}, // 9A\n {mn:\"SHS\",am:\"AAAA,y\",nb:3,il:1,c1:0,c2:0}, // 9B\n {mn:\"SHY\",am:\"AAAA,x\",nb:3,il:1,c1:0,c2:0}, // 9C\n {mn:\"STA\",am:\"AAAA,x\",nb:3,il:0,c1:5,c2:0}, // 9D\n {mn:\"SHX\",am:\"AAAA,y\",nb:3,il:1,c1:0,c2:0}, // 9E\n {mn:\"SHA\",am:\"AAAA,y\",nb:3,il:1,c1:0,c2:0}, // 9F\n {mn:\"LDY\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // A0\n {mn:\"LDA\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // A1\n {mn:\"LDX\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // A2\n {mn:\"LAX\",am:\"(aa,x)\",nb:2,il:1,c1:6,c2:1}, // A3\n {mn:\"LDY\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // A4\n {mn:\"LDA\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // A5\n {mn:\"LDX\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // A6\n {mn:\"LAX\",am:\"aa\",nb:2,il:1,c1:3,c2:0}, // A7\n {mn:\"TAY\",am:\"\",nb:1,il:0,c1:2,c2:0}, // A8\n {mn:\"LDA\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // A9\n {mn:\"TAX\",am:\"\",nb:1,il:0,c1:2,c2:0}, // AA\n {mn:\"LXA\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // AB\n {mn:\"LDY\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // AC\n {mn:\"LDA\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // AD\n {mn:\"LDX\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // AE\n {mn:\"LAX\",am:\"AAAA\",nb:3,il:1,c1:4,c2:0}, // AF\n {mn:\"BCS\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // B0\n {mn:\"LDA\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // B1\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // B2\n {mn:\"LAX\",am:\"(aa),y\",nb:2,il:1,c1:5,c2:1}, // B3\n {mn:\"LDY\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // B4\n {mn:\"LDA\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // B5\n {mn:\"LDX\",am:\"aa,y\",nb:2,il:0,c1:4,c2:0}, // B6\n {mn:\"LAX\",am:\"aa,y\",nb:2,il:1,c1:4,c2:1}, // B7\n {mn:\"CLV\",am:\"\",nb:1,il:0,c1:2,c2:0}, // B8\n {mn:\"LDA\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // B9\n {mn:\"TSX\",am:\"\",nb:1,il:0,c1:2,c2:0}, // BA\n {mn:\"LAS\",am:\"AAAA,y\",nb:3,il:1,c1:0,c2:0}, // BB\n {mn:\"LDY\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // BC\n {mn:\"LDA\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // BD\n {mn:\"LDX\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // BE\n {mn:\"LAX\",am:\"AAAA,y\",nb:3,il:1,c1:4,c2:1}, // BF\n {mn:\"CPY\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // C0\n {mn:\"CMP\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // C1\n {mn:\"NOP\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // C2\n {mn:\"DCP\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // C3\n {mn:\"CPY\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // C4\n {mn:\"CMP\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // C5\n {mn:\"DEC\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // C6\n {mn:\"DCP\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // C7\n {mn:\"INY\",am:\"\",nb:1,il:0,c1:2,c2:0}, // C8\n {mn:\"CMP\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // C9\n {mn:\"DEX\",am:\"\",nb:1,il:0,c1:2,c2:0}, // CA\n {mn:\"SBX\",am:\"#aa\",nb:2,il:1,c1:2,c2:0}, // CB\n {mn:\"CPY\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // CC\n {mn:\"CMP\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // CD\n {mn:\"DEC\",am:\"AAAA\",nb:3,il:0,c1:3,c2:0}, // CE\n {mn:\"DCP\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // CF\n {mn:\"BNE\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // D0\n {mn:\"CMP\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // D1\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // D2\n {mn:\"DCP\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // D3\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // D4\n {mn:\"CMP\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // D5\n {mn:\"DEC\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // D6\n {mn:\"DCP\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // D7\n {mn:\"CLD\",am:\"\",nb:1,il:0,c1:2,c2:0}, // D8\n {mn:\"CMP\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // D9\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // DA\n {mn:\"DCP\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // DB\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // DC\n {mn:\"CMP\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // DD\n {mn:\"DEC\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // DE\n {mn:\"DCP\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // DF\n {mn:\"CPX\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // E0\n {mn:\"SBC\",am:\"(aa,x)\",nb:2,il:0,c1:6,c2:0}, // E1\n {mn:\"NOP\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // E2\n {mn:\"ISB\",am:\"(aa,x)\",nb:2,il:1,c1:8,c2:1}, // E3\n {mn:\"CPX\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // E4\n {mn:\"SBC\",am:\"aa\",nb:2,il:0,c1:3,c2:0}, // E5\n {mn:\"INC\",am:\"aa\",nb:2,il:0,c1:5,c2:0}, // E6\n {mn:\"ISB\",am:\"aa\",nb:2,il:1,c1:5,c2:0}, // E7\n {mn:\"INX\",am:\"\",nb:1,il:0,c1:2,c2:0}, // E8\n {mn:\"SBC\",am:\"#aa\",nb:2,il:0,c1:2,c2:0}, // E9\n {mn:\"NOP\",am:\"\",nb:1,il:0,c1:2,c2:0}, // EA\n {mn:\"SBC\",am:\"#aa\",nb:2,il:1,c1:0,c2:0}, // EB\n {mn:\"CPX\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // EC\n {mn:\"SBC\",am:\"AAAA\",nb:3,il:0,c1:4,c2:0}, // ED\n {mn:\"INC\",am:\"AAAA\",nb:3,il:0,c1:6,c2:0}, // EE\n {mn:\"ISB\",am:\"AAAA\",nb:3,il:1,c1:6,c2:0}, // EF\n {mn:\"BEQ\",am:\"branch\",nb:2,il:0,c1:2,c2:2}, // F0\n {mn:\"SBC\",am:\"(aa),y\",nb:2,il:0,c1:5,c2:1}, // F1\n {mn:\"KIL\",am:\"\",nb:1,il:1,c1:0,c2:0}, // F2\n {mn:\"ISB\",am:\"(aa),y\",nb:2,il:1,c1:8,c2:1}, // F3\n {mn:\"NOP\",am:\"aa,x\",nb:2,il:1,c1:4,c2:0}, // F4\n {mn:\"SBC\",am:\"aa,x\",nb:2,il:0,c1:4,c2:0}, // F5\n {mn:\"INC\",am:\"aa,x\",nb:2,il:0,c1:6,c2:0}, // F6\n {mn:\"ISB\",am:\"aa,x\",nb:2,il:1,c1:6,c2:1}, // F7\n {mn:\"SED\",am:\"\",nb:1,il:0,c1:2,c2:0}, // F8\n {mn:\"SBC\",am:\"AAAA,y\",nb:3,il:0,c1:4,c2:1}, // F9\n {mn:\"NOP\",am:\"\",nb:1,il:1,c1:0,c2:0}, // FA\n {mn:\"ISB\",am:\"AAAA,y\",nb:3,il:1,c1:7,c2:1}, // FB\n {mn:\"NOP\",am:\"AAAA,x\",nb:3,il:1,c1:4,c2:1}, // FC\n {mn:\"SBC\",am:\"AAAA,x\",nb:3,il:0,c1:4,c2:1}, // FD\n {mn:\"INC\",am:\"AAAA,x\",nb:3,il:0,c1:7,c2:0}, // FE\n {mn:\"ISB\",am:\"AAAA,x\",nb:3,il:1,c1:7,c2:1}, // FF\n];\n\nexport function disassemble6502(pc:number, b0:number, b1:number, b2:number) : {line:string, nbytes:number, isaddr:boolean} {\n\n var op = OPS_6502[b0];\n if (op == null) return {line:\"???\", nbytes:1, isaddr:false};\n var s = op.mn;\n var am = op.am;\n var isaddr = false;\n if (am == 'branch') {\n var offset = (b1 < 0x80) ? (pc+2+b1) : (pc+2-(256-b1));\n offset &= 0xffff;\n am = '$'+hex(offset, 4);\n isaddr = true;\n } else {\n am = am.replace('aa','$'+hex(b1, 2));\n am = am.replace('AAAA','$'+hex(b1+(b2<<8), 4));\n if (am.indexOf('#') < 0 && am.indexOf('$') >= 0)\n isaddr = true;\n }\n return {line:op.mn + \" \" + am, nbytes:op.nb, isaddr:isaddr};\n};\n", "// Generated by CoffeeScript 1.9.3\n\nimport { CPU, Bus, InstructionBased, IOBusConnected, SavesState, Interruptable } from \"../devices\";\n\n///////////////////////////////////////////////////////////////////////////////\n/// @file Z80.js\n///\n/// @brief Emulator for the Zilog Z80 microprocessor\n///\n/// @author Matthew Howell\n///\n/// @remarks\n/// This module is a simple, straightforward instruction interpreter.\n/// There is no fancy dynamic recompilation or cycle-accurate emulation.\n/// The author believes that this should be sufficient for any emulator that\n/// would be feasible to write in JavaScript anyway.\n/// The code and the comments in this file assume that the reader is familiar\n/// with the Z80 architecture. If you're not, here are some references I use:\n/// http://clrhome.org/table/ - Z80 instruction set tables\n/// http://www.zilog.com/docs/z80/um0080.pdf - The official manual\n/// http://www.myquest.nl/z80undocumented/z80-documented-v0.91.pdf\n/// - The Undocumented Z80, Documented\n///\n/// @copyright (c) 2013 Matthew Howell\n/// This code is released under the MIT license,\n/// a copy of which is available in the associated README.md file,\n/// or at http://opensource.org/licenses/MIT\n///////////////////////////////////////////////////////////////////////////////\n\n///////////////////////////////////////////////////////////////////////////////\n/// We'll begin with the object constructor and the public API functions.\n///////////////////////////////////////////////////////////////////////////////\nfunction FastZ80(coreParameter)\n{\n // Obviously we'll be needing the core object's functions again.\n const core = coreParameter;\n \n // The argument to this constructor should be an object containing 4 functions:\n // mem_read(address) should return the byte at the given memory address,\n // mem_write(address, value) should write the given value to the given memory address,\n // io_read(port) should read a return a byte read from the given I/O port,\n // io_write(port, value) should write the given byte to the given I/O port.\n // If any of those functions is missing, this module cannot run.\n if (!core || (typeof core.mem_read !== \"function\") || (typeof core.mem_write !== \"function\") ||\n (typeof core.io_read !== \"function\") || (typeof core.io_write !== \"function\"))\n throw(\"Z80: Core object is missing required functions.\");\n \n // All right, let's initialize the registers.\n // First, the standard 8080 registers.\n let a = 0x00;\n let b = 0x00;\n let c = 0x00;\n let d = 0x00;\n let e = 0x00;\n let h = 0x00;\n let l = 0x00;\n // Now the special Z80 copies of the 8080 registers\n // (the ones used for the SWAP instruction and such).\n let a_prime = 0x00;\n let b_prime = 0x00;\n let c_prime = 0x00;\n let d_prime = 0x00;\n let e_prime = 0x00;\n let h_prime = 0x00;\n let l_prime = 0x00;\n // And now the Z80 index registers.\n let ix = 0x0000;\n let iy = 0x0000;\n // Then the \"utility\" registers: the interrupt vector,\n // the memory refresh, the stack pointer, and the program counter.\n let i = 0x00;\n let r = 0x00;\n let sp = 0xdff0;\n let pc = 0x0000;\n // We don't keep an F register for the flags,\n // because most of the time we're only accessing a single flag,\n // so we optimize for that case and use utility functions\n // for the rarer occasions when we need to access the whole register.\n let flags = {S:0, Z:0, Y:0, H:0, X:0, P:0, N:0, C:0};\n let flags_prime = {S:0, Z:0, Y:0, H:0, X:0, P:0, N:0, C:0};\n // And finally we have the interrupt mode and flip-flop registers.\n let imode = 0;\n let iff1 = 0;\n let iff2 = 0;\n \n // These are all specific to this implementation, not Z80 features.\n // Keep track of whether we've had a HALT instruction called.\n let halted = false;\n // EI and DI wait one instruction before they take effect;\n // these flags tell us when we're in that wait state.\n let do_delayed_di = false;\n let do_delayed_ei = false;\n // This tracks the number of cycles spent in a single instruction run,\n // including processing any prefixes and handling interrupts.\n let cycle_counter = 0;\n \n function getState():Z80State {\n return {\n PC:pc,\n SP:sp,\n IX:ix,\n IY:iy,\n AF:(a<<8)+get_flags_register(),\n BC:(b<<8)+c,\n DE:(d<<8)+e,\n HL:(h<<8)+l,\n AF_:(a_prime<<8)+get_flags_prime(),\n BC_:(b_prime<<8)+c_prime,\n DE_:(d_prime<<8)+e_prime,\n HL_:(h_prime<<8)+l_prime,\n IR:(i<<8)+r,\n im : imode,\n iff1 : iff1,\n iff2 : iff2,\n halted : halted,\n do_delayed_di : do_delayed_di,\n do_delayed_ei : do_delayed_ei,\n cycle_counter : cycle_counter\n }; \n }\n\n function setState(state:Z80State) {\n pc = state.PC;\n sp = state.SP;\n ix = state.IX;\n iy = state.IY;\n a = (state.AF >> 8) & 0xff;\n set_flags_register(state.AF);\n b = (state.BC >> 8) & 0xff;\n c = state.BC & 0xff;\n d = (state.DE >> 8) & 0xff;\n e = state.DE & 0xff;\n h = (state.HL >> 8) & 0xff;\n l = state.HL & 0xff;\n a_prime = (state.AF_ >> 8) & 0xff;\n set_flags_prime(state.AF_);\n b_prime = (state.BC_ >> 8) & 0xff;\n c_prime = state.BC_ & 0xff;\n d_prime = (state.DE_ >> 8) & 0xff;\n e_prime = state.DE_ & 0xff;\n h_prime = (state.HL_ >> 8) & 0xff;\n l_prime = state.HL_ & 0xff;\n i = (state.IR >> 8) & 0xff;\n r = state.IR & 0xff;\n imode = state.im;\n iff1 = state.iff1;\n iff2 = state.iff2;\n halted = state.halted;\n do_delayed_di = state.do_delayed_di;\n do_delayed_ei = state.do_delayed_ei;\n cycle_counter = state.cycle_counter;\n }\n\n///////////////////////////////////////////////////////////////////////////////\n/// @public reset\n///\n/// @brief Re-initialize the processor as if a reset or power on had occured\n///////////////////////////////////////////////////////////////////////////////\nlet reset = function()\n{\n // These registers are the ones that have predictable states\n // immediately following a power-on or a reset.\n // The others are left alone, because their states are unpredictable.\n sp = 0xdff0;\n pc = 0x0000;\n a = 0x00;\n r = 0x00;\n set_flags_register(0);\n // Start up with interrupts disabled.\n imode = 0;\n iff1 = 0;\n iff2 = 0;\n // Don't start halted or in a delayed DI or EI.\n halted = false;\n do_delayed_di = false;\n do_delayed_ei = false;\n // Obviously we've not used any cycles yet.\n cycle_counter = 0;\n};\n\n///////////////////////////////////////////////////////////////////////////////\n/// @public run_instruction\n///\n/// @brief Runs a single instruction\n///\n/// @return The number of T cycles the instruction took to run,\n/// plus any time that went into handling interrupts that fired\n/// while this instruction was executing\n///////////////////////////////////////////////////////////////////////////////\nlet run_instruction = function()\n{\n if (!halted)\n {\n // If the previous instruction was a DI or an EI,\n // we'll need to disable or enable interrupts\n // after whatever instruction we're about to run is finished.\n var doing_delayed_di = false, doing_delayed_ei = false;\n if (do_delayed_di)\n {\n do_delayed_di = false;\n doing_delayed_di = true;\n }\n else if (do_delayed_ei)\n {\n do_delayed_ei = false;\n doing_delayed_ei = true;\n }\n\n // R is incremented at the start of every instruction cycle,\n // before the instruction actually runs.\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n \n // Read the byte at the PC and run the instruction it encodes.\n var opcode = core.mem_read(pc);\n decode_instruction(opcode);\n pc = (pc + 1) & 0xffff;\n \n // Actually do the delayed interrupt disable/enable if we have one.\n if (doing_delayed_di)\n {\n iff1 = 0;\n iff2 = 0;\n //console.log(\"DI\",pc);\n }\n else if (doing_delayed_ei)\n {\n iff1 = 1;\n iff2 = 1;\n //console.log(\"EI\",pc);\n }\n \n // And finally clear out the cycle counter for the next instruction\n // before returning it to the emulator core.\n var retval = cycle_counter;\n cycle_counter = 0;\n return retval;\n }\n else\n {\n // While we're halted, claim that we spent a cycle doing nothing,\n // so that the rest of the emulator can still proceed.\n return 1;\n }\n};\n\n///////////////////////////////////////////////////////////////////////////////\n/// @public interrupt\n///\n/// @brief Simulates pulsing the processor's INT (or NMI) pin\n///\n/// @param non_maskable - true if this is a non-maskable interrupt\n/// @param data - the value to be placed on the data bus, if needed\n///////////////////////////////////////////////////////////////////////////////\nlet interrupt = function(non_maskable:boolean, data:number) : boolean\n{\n //console.log(non_maskable, data, iff1, iff2, do_delayed_ei, do_delayed_di);\n if (non_maskable)\n {\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n // Non-maskable interrupts are always handled the same way;\n // clear IFF1 and then do a CALL 0x0066.\n // Also, all interrupts reset the HALT state.\n halted = false;\n iff2 = iff1;\n iff1 = 0;\n push_word(pc);\n pc = 0x66;\n cycle_counter += 11;\n return true;\n }\n else if (iff1)\n {\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n \n halted = false;\n iff1 = 0;\n iff2 = 0;\n \n if (imode === 0)\n {\n // In the 8080-compatible interrupt mode,\n // decode the content of the data bus as an instruction and run it.\n pc = (pc - 1) & 0xffff; //SEH: so do_reset() pushes right value\n decode_instruction(data);\n pc = (pc + 1) & 0xffff; //SEH: so do_reset() pushes right value\n cycle_counter += 2;\n }\n else if (imode === 1)\n {\n // Mode 1 is always just RST 0x38.\n push_word(pc);\n pc = 0x38;\n cycle_counter += 13;\n }\n else if (imode === 2)\n {\n // Mode 2 uses the value on the data bus as in index\n // into the vector table pointer to by the I register.\n push_word(pc);\n // The Z80 manual says that this address must be 2-byte aligned,\n // but it doesn't appear that this is actually the case on the hardware,\n // so we don't attempt to enforce that here.\n var vector_address = ((i << 8) | data);\n pc = core.mem_read(vector_address) | \n (core.mem_read((vector_address + 1) & 0xffff) << 8);\n \n cycle_counter += 19;\n }\n //console.log(imode,data,pc);\n return true;\n }\n};\n\n///////////////////////////////////////////////////////////////////////////////\n/// The public API functions end here.\n///\n/// What begins here are just general utility functions, used variously.\n///////////////////////////////////////////////////////////////////////////////\nlet decode_instruction = function(opcode)\n{\n // The register-to-register loads and ALU instructions\n // are all so uniform that we can decode them directly\n // instead of going into the instruction array for them.\n // This function gets the operand for all of these instructions.\n var get_operand = function(opcode)\n {\n return ((opcode & 0x07) === 0) ? b :\n ((opcode & 0x07) === 1) ? c :\n ((opcode & 0x07) === 2) ? d :\n ((opcode & 0x07) === 3) ? e :\n ((opcode & 0x07) === 4) ? h :\n ((opcode & 0x07) === 5) ? l :\n ((opcode & 0x07) === 6) ? core.mem_read(l | (h << 8)) : a;\n };\n\n // Handle HALT right up front, because it fouls up our LD decoding\n // by falling where LD (HL), (HL) ought to be.\n if (opcode === 0x76)\n {\n halted = true;\n }\n else if ((opcode >= 0x40) && (opcode < 0x80))\n {\n // This entire range is all 8-bit register loads.\n // Get the operand and assign it to the correct destination.\n var operand = get_operand(opcode);\n \n if (((opcode & 0x38) >>> 3) === 0)\n b = operand;\n else if (((opcode & 0x38) >>> 3) === 1)\n c = operand;\n else if (((opcode & 0x38) >>> 3) === 2)\n d = operand;\n else if (((opcode & 0x38) >>> 3) === 3)\n e = operand;\n else if (((opcode & 0x38) >>> 3) === 4)\n h = operand;\n else if (((opcode & 0x38) >>> 3) === 5)\n l = operand;\n else if (((opcode & 0x38) >>> 3) === 6)\n core.mem_write(l | (h << 8), operand);\n else if (((opcode & 0x38) >>> 3) === 7)\n a = operand;\n }\n else if ((opcode >= 0x80) && (opcode < 0xc0))\n {\n // These are the 8-bit register ALU instructions.\n // We'll get the operand and then use this \"jump table\"\n // to call the correct utility function for the instruction.\n var operand = get_operand(opcode),\n op_array = [do_add, do_adc, do_sub, do_sbc,\n do_and, do_xor, do_or, do_cp];\n \n op_array[(opcode & 0x38) >>> 3]( operand);\n }\n else\n {\n // This is one of the less formulaic instructions;\n // we'll get the specific function for it from our array.\n var func = instructions[opcode];\n func();\n }\n \n // Update the cycle counter with however many cycles\n // the base instruction took.\n // If this was a prefixed instruction, then\n // the prefix handler has added its extra cycles already.\n cycle_counter += cycle_counts[opcode];\n};\n\nlet get_signed_offset_byte = function(value)\n{\n // This function requires some explanation.\n // We just use JavaScript Number variables for our registers,\n // not like a typed array or anything.\n // That means that, when we have a byte value that's supposed\n // to represent a signed offset, the value we actually see\n // isn't signed at all, it's just a small integer.\n // So, this function converts that byte into something JavaScript\n // will recognize as signed, so we can easily do arithmetic with it.\n // First, we clamp the value to a single byte, just in case.\n value &= 0xff;\n // We don't have to do anything if the value is positive.\n if (value & 0x80)\n {\n // But if the value is negative, we need to manually un-two's-compliment it.\n // I'm going to assume you can figure out what I meant by that,\n // because I don't know how else to explain it.\n // We could also just do value |= 0xffffff00, but I prefer\n // not caring how many bits are in the integer representation\n // of a JavaScript number in the currently running browser.\n value = -((0xff & ~value) + 1);\n }\n return value;\n};\n\nlet get_flags_register = function()\n{\n // We need the whole F register for some reason.\n // probably a PUSH AF instruction,\n // so make the F register out of our separate flags.\n return (flags.S << 7) |\n (flags.Z << 6) |\n (flags.Y << 5) |\n (flags.H << 4) |\n (flags.X << 3) |\n (flags.P << 2) |\n (flags.N << 1) |\n (flags.C);\n};\n\nlet get_flags_prime = function()\n{\n // This is the same as the above for the F' register.\n return (flags_prime.S << 7) |\n (flags_prime.Z << 6) |\n (flags_prime.Y << 5) |\n (flags_prime.H << 4) |\n (flags_prime.X << 3) |\n (flags_prime.P << 2) |\n (flags_prime.N << 1) |\n (flags_prime.C);\n};\n\nlet set_flags_register = function(operand)\n{\n // We need to set the F register, probably for a POP AF,\n // so break out the given value into our separate flags.\n flags.S = (operand & 0x80) >>> 7;\n flags.Z = (operand & 0x40) >>> 6;\n flags.Y = (operand & 0x20) >>> 5;\n flags.H = (operand & 0x10) >>> 4;\n flags.X = (operand & 0x08) >>> 3;\n flags.P = (operand & 0x04) >>> 2;\n flags.N = (operand & 0x02) >>> 1;\n flags.C = (operand & 0x01);\n};\n\nlet set_flags_prime = function(operand)\n{\n // Again, this is the same as the above for F'.\n flags_prime.S = (operand & 0x80) >>> 7;\n flags_prime.Z = (operand & 0x40) >>> 6;\n flags_prime.Y = (operand & 0x20) >>> 5;\n flags_prime.H = (operand & 0x10) >>> 4;\n flags_prime.X = (operand & 0x08) >>> 3;\n flags_prime.P = (operand & 0x04) >>> 2;\n flags_prime.N = (operand & 0x02) >>> 1;\n flags_prime.C = (operand & 0x01);\n};\n\nlet update_xy_flags = function(result)\n{\n // Most of the time, the undocumented flags\n // (sometimes called X and Y, or 3 and 5),\n // take their values from the corresponding bits\n // of the result of the instruction,\n // or from some other related value.\n // This is a utility function to set those flags based on those bits.\n flags.Y = (result & 0x20) >>> 5;\n flags.X = (result & 0x08) >>> 3;\n};\n\nlet get_parity = function(value)\n{\n // We could try to actually calculate the parity every time,\n // but why calculate what you can pre-calculate?\n var parity_bits = [\n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,\n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, \n 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1\n ];\n return parity_bits[value];\n};\n\nlet push_word = function(operand)\n{\n // Pretty obvious what this function does; given a 16-bit value,\n // decrement the stack pointer, write the high byte to the new\n // stack pointer location, then repeat for the low byte.\n sp = (sp - 1) & 0xffff;\n core.mem_write(sp, (operand & 0xff00) >>> 8);\n sp = (sp - 1) & 0xffff;\n core.mem_write(sp, operand & 0x00ff);\n};\n\nlet pop_word = function()\n{\n // Again, not complicated; read a byte off the top of the stack,\n // increment the stack pointer, rinse and repeat.\n var retval = core.mem_read(sp) & 0xff;\n sp = (sp + 1) & 0xffff;\n retval |= core.mem_read(sp) << 8;\n sp = (sp + 1) & 0xffff;\n return retval;\n};\n\n///////////////////////////////////////////////////////////////////////////////\n/// Now, the way most instructions work in this emulator is that they set up\n/// their operands according to their addressing mode, and then they call a\n/// utility function that handles all variations of that instruction.\n/// Those utility functions begin here.\n///////////////////////////////////////////////////////////////////////////////\nlet do_conditional_absolute_jump = function(condition)\n{\n // This function implements the JP [condition],nn instructions.\n if (condition)\n {\n // We're taking this jump, so write the new PC,\n // and then decrement the thing we just wrote,\n // because the instruction decoder increments the PC\n // unconditionally at the end of every instruction\n // and we need to counteract that so we end up at the jump target.\n pc = core.mem_read((pc + 1) & 0xffff) |\n (core.mem_read((pc + 2) & 0xffff) << 8);\n pc = (pc - 1) & 0xffff;\n }\n else\n {\n // We're not taking this jump, just move the PC past the operand.\n pc = (pc + 2) & 0xffff;\n }\n};\n\nlet do_conditional_relative_jump = function(condition)\n{\n // This function implements the JR [condition],n instructions.\n if (condition)\n {\n // We need a few more cycles to actually take the jump.\n cycle_counter += 5;\n // Calculate the offset specified by our operand.\n var offset = get_signed_offset_byte(core.mem_read((pc + 1) & 0xffff));\n // Add the offset to the PC, also skipping past this instruction.\n pc = (pc + offset + 1) & 0xffff;\n }\n else\n {\n // No jump happening, just skip the operand.\n pc = (pc + 1) & 0xffff;\n }\n};\n\nlet do_conditional_call = function(condition)\n{\n // This function is the CALL [condition],nn instructions.\n // If you've seen the previous functions, you know this drill.\n if (condition)\n {\n cycle_counter += 7;\n push_word((pc + 3) & 0xffff);\n pc = core.mem_read((pc + 1) & 0xffff) |\n (core.mem_read((pc + 2) & 0xffff) << 8);\n pc = (pc - 1) & 0xffff;\n }\n else\n {\n pc = (pc + 2) & 0xffff;\n }\n};\n\nlet do_conditional_return = function(condition)\n{\n if (condition)\n {\n cycle_counter += 6;\n pc = (pop_word() - 1) & 0xffff;\n }\n};\n\nlet do_reset = function(address)\n{\n // The RST [address] instructions go through here.\n push_word((pc + 1) & 0xffff);\n pc = (address - 1) & 0xffff;\n};\n\nlet do_add = function(operand)\n{\n // This is the ADD A, [operand] instructions.\n // We'll do the literal addition, which includes any overflow,\n // so that we can more easily figure out whether we had\n // an overflow or a carry and set the flags accordingly.\n var result = a + operand;\n \n // The great majority of the work for the arithmetic instructions\n // turns out to be setting the flags rather than the actual operation.\n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = (((operand & 0x0f) + (a & 0x0f)) & 0x10) ? 1 : 0;\n // An overflow has happened if the sign bits of the accumulator and the operand\n // don't match the sign bit of the result value.\n flags.P = ((a & 0x80) === (operand & 0x80)) && ((a & 0x80) !== (result & 0x80)) ? 1 : 0;\n flags.N = 0;\n flags.C = (result & 0x100) ? 1 : 0;\n \n a = result & 0xff;\n update_xy_flags(a);\n};\n\nlet do_adc = function(operand)\n{\n var result = a + operand + flags.C;\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = (((operand & 0x0f) + (a & 0x0f) + flags.C) & 0x10) ? 1 : 0;\n flags.P = ((a & 0x80) === (operand & 0x80)) && ((a & 0x80) !== (result & 0x80)) ? 1 : 0;\n flags.N = 0;\n flags.C = (result & 0x100) ? 1 : 0;\n \n a = result & 0xff;\n update_xy_flags(a);\n};\n\nlet do_sub = function(operand)\n{\n var result = a - operand;\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = (((a & 0x0f) - (operand & 0x0f)) & 0x10) ? 1 : 0;\n flags.P = ((a & 0x80) !== (operand & 0x80)) && ((a & 0x80) !== (result & 0x80)) ? 1 : 0;\n flags.N = 1;\n flags.C = (result & 0x100) ? 1 : 0;\n \n a = result & 0xff;\n update_xy_flags(a);\n};\n\nlet do_sbc = function(operand)\n{\n var result = a - operand - flags.C;\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = (((a & 0x0f) - (operand & 0x0f) - flags.C) & 0x10) ? 1 : 0;\n flags.P = ((a & 0x80) !== (operand & 0x80)) && ((a & 0x80) !== (result & 0x80)) ? 1 : 0;\n flags.N = 1;\n flags.C = (result & 0x100) ? 1 : 0;\n \n a = result & 0xff;\n update_xy_flags(a);\n};\n\nlet do_cp = function(operand)\n{\n // A compare instruction is just a subtraction that doesn't save the value,\n // so we implement it as... a subtraction that doesn't save the value.\n var temp = a;\n do_sub(operand);\n a = temp;\n // Since this instruction has no \"result\" value, the undocumented flags\n // are set based on the operand instead.\n update_xy_flags(operand);\n};\n\nlet do_and = function(operand)\n{\n // The logic instructions are all pretty straightforward.\n a &= operand & 0xff;\n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = !a ? 1 : 0;\n flags.H = 1;\n flags.P = get_parity(a);\n flags.N = 0;\n flags.C = 0;\n update_xy_flags(a);\n};\n\nlet do_or = function(operand)\n{\n a = (operand | a) & 0xff;\n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = !a ? 1 : 0;\n flags.H = 0;\n flags.P = get_parity(a);\n flags.N = 0;\n flags.C = 0;\n update_xy_flags(a);\n};\n\nlet do_xor = function(operand)\n{\n a = (operand ^ a) & 0xff;\n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = !a ? 1 : 0;\n flags.H = 0;\n flags.P = get_parity(a);\n flags.N = 0;\n flags.C = 0;\n update_xy_flags(a);\n};\n\nlet do_inc = function(operand)\n{\n var result = operand + 1;\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = ((operand & 0x0f) === 0x0f) ? 1 : 0;\n // It's a good deal easier to detect overflow for an increment/decrement.\n flags.P = (operand === 0x7f) ? 1 : 0;\n flags.N = 0;\n \n result &= 0xff;\n update_xy_flags(result);\n \n return result;\n};\n\nlet do_dec = function(operand)\n{\n var result = operand - 1;\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = !(result & 0xff) ? 1 : 0;\n flags.H = ((operand & 0x0f) === 0x00) ? 1 : 0;\n flags.P = (operand === 0x80) ? 1 : 0;\n flags.N = 1;\n \n result &= 0xff;\n update_xy_flags(result);\n \n return result;\n};\n\nlet do_hl_add = function(operand)\n{\n // The HL arithmetic instructions are the same as the A ones,\n // just with twice as many bits happening.\n var hl = l | (h << 8), result = hl + operand;\n \n flags.N = 0;\n flags.C = (result & 0x10000) ? 1 : 0;\n flags.H = (((hl & 0x0fff) + (operand & 0x0fff)) & 0x1000) ? 1 : 0;\n \n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n\n update_xy_flags(h);\n};\n\nlet do_hl_adc = function(operand)\n{\n operand += flags.C;\n var hl = l | (h << 8), result = hl + operand;\n \n flags.S = (result & 0x8000) ? 1 : 0;\n flags.Z = !(result & 0xffff) ? 1 : 0;\n flags.H = (((hl & 0x0fff) + (operand & 0x0fff)) & 0x1000) ? 1 : 0;\n flags.P = ((hl & 0x8000) === (operand & 0x8000)) && ((result & 0x8000) !== (hl & 0x8000)) ? 1 : 0;\n flags.N = 0;\n flags.C = (result & 0x10000) ? 1 : 0;\n \n l = result & 0xff;\n h = (result >>> 8) & 0xff;\n \n update_xy_flags(h);\n};\n\nlet do_hl_sbc = function(operand)\n{\n operand += flags.C;\n var hl = l | (h << 8), result = hl - operand;\n \n flags.S = (result & 0x8000) ? 1 : 0;\n flags.Z = !(result & 0xffff) ? 1 : 0;\n flags.H = (((hl & 0x0fff) - (operand & 0x0fff)) & 0x1000) ? 1 : 0;\n flags.P = ((hl & 0x8000) !== (operand & 0x8000)) && ((result & 0x8000) !== (hl & 0x8000)) ? 1 : 0;\n flags.N = 1;\n flags.C = (result & 0x10000) ? 1 : 0;\n \n l = result & 0xff;\n h = (result >>> 8) & 0xff;\n \n update_xy_flags(h);\n};\n\nlet do_in = function(port)\n{\n var result = core.io_read(port);\n \n flags.S = (result & 0x80) ? 1 : 0;\n flags.Z = result ? 0 : 1;\n flags.H = 0;\n flags.P = get_parity(result) ? 1 : 0;\n flags.N = 0;\n update_xy_flags(result);\n \n return result;\n};\n\nlet do_neg = function()\n{\n // This instruction is defined to not alter the register if it === 0x80.\n if (a !== 0x80)\n {\n // This is a signed operation, so convert A to a signed value.\n a = get_signed_offset_byte(a);\n \n a = (-a) & 0xff;\n }\n \n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = !a ? 1 : 0;\n flags.H = (((-a) & 0x0f) > 0) ? 1 : 0;\n flags.P = (a === 0x80) ? 1 : 0;\n flags.N = 1;\n flags.C = a ? 1 : 0;\n update_xy_flags(a);\n};\n\nlet do_ldi = function()\n{\n // Copy the value that we're supposed to copy.\n var read_value = core.mem_read(l | (h << 8));\n core.mem_write(e | (d << 8), read_value);\n \n // Increment DE and HL, and decrement BC.\n var result = (e | (d << 8)) + 1;\n e = result & 0xff;\n d = (result & 0xff00) >>> 8;\n result = (l | (h << 8)) + 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n result = (c | (b << 8)) - 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n \n flags.H = 0;\n flags.P = (c || b) ? 1 : 0;\n flags.N = 0;\n flags.Y = ((a + read_value) & 0x02) >>> 1;\n flags.X = ((a + read_value) & 0x08) >>> 3;\n};\n\nlet do_cpi = function()\n{\n var temp_carry = flags.C;\n var read_value = core.mem_read(l | (h << 8))\n do_cp(read_value);\n flags.C = temp_carry;\n flags.Y = ((a - read_value - flags.H) & 0x02) >>> 1;\n flags.X = ((a - read_value - flags.H) & 0x08) >>> 3;\n \n var result = (l | (h << 8)) + 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n result = (c | (b << 8)) - 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n \n flags.P = result ? 1 : 0;\n};\n\nlet do_ini = function()\n{\n b = do_dec(b);\n \n core.mem_write(l | (h << 8), core.io_read((b << 8) | c));\n \n var result = (l | (h << 8)) + 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n\n flags.N = 1;\n};\n\nlet do_outi = function()\n{\n core.io_write((b << 8) | c, core.mem_read(l | (h << 8)));\n \n var result = (l | (h << 8)) + 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n \n b = do_dec(b);\n flags.N = 1;\n};\n\nlet do_ldd = function()\n{\n flags.N = 0;\n flags.H = 0;\n \n var read_value = core.mem_read(l | (h << 8));\n core.mem_write(e | (d << 8), read_value);\n \n var result = (e | (d << 8)) - 1;\n e = result & 0xff;\n d = (result & 0xff00) >>> 8;\n result = (l | (h << 8)) - 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n result = (c | (b << 8)) - 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n \n flags.P = (c || b) ? 1 : 0;\n flags.Y = ((a + read_value) & 0x02) >>> 1;\n flags.X = ((a + read_value) & 0x08) >>> 3;\n};\n\nlet do_cpd = function()\n{\n var temp_carry = flags.C\n var read_value = core.mem_read(l | (h << 8))\n do_cp(read_value);\n flags.C = temp_carry;\n flags.Y = ((a - read_value - flags.H) & 0x02) >>> 1;\n flags.X = ((a - read_value - flags.H) & 0x08) >>> 3;\n \n var result = (l | (h << 8)) - 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n result = (c | (b << 8)) - 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n \n flags.P = result ? 1 : 0;\n};\n\nlet do_ind = function()\n{\n b = do_dec(b);\n \n core.mem_write(l | (h << 8), core.io_read((b << 8) | c));\n \n var result = (l | (h << 8)) - 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n \n flags.N = 1;\n};\n\nlet do_outd = function()\n{\n core.io_write((b << 8) | c, core.mem_read(l | (h << 8)));\n \n var result = (l | (h << 8)) - 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n \n b = do_dec(b);\n flags.N = 1;\n};\n\nlet do_rlc = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = (operand & 0x80) >>> 7;\n operand = ((operand << 1) | flags.C) & 0xff;\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n \n return operand;\n};\n\nlet do_rrc = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = operand & 1;\n operand = ((operand >>> 1) & 0x7f) | (flags.C << 7);\n \n flags.Z = !(operand & 0xff) ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n \n return operand & 0xff;\n};\n\nlet do_rl = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n var temp = flags.C;\n flags.C = (operand & 0x80) >>> 7;\n operand = ((operand << 1) | temp) & 0xff;\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n\n return operand;\n};\n\nlet do_rr = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n var temp = flags.C;\n flags.C = operand & 1;\n operand = ((operand >>> 1) & 0x7f) | (temp << 7);\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n\n return operand;\n};\n\nlet do_sla = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = (operand & 0x80) >>> 7;\n operand = (operand << 1) & 0xff;\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n \n return operand;\n};\n\nlet do_sra = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = operand & 1;\n operand = ((operand >>> 1) & 0x7f) | (operand & 0x80);\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n \n return operand;\n};\n\nlet do_sll = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = (operand & 0x80) >>> 7;\n operand = ((operand << 1) & 0xff) | 1;\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = (operand & 0x80) ? 1 : 0;\n update_xy_flags(operand);\n \n return operand;\n};\n\nlet do_srl = function(operand)\n{\n flags.N = 0;\n flags.H = 0;\n \n flags.C = operand & 1;\n operand = (operand >>> 1) & 0x7f;\n \n flags.Z = !operand ? 1 : 0;\n flags.P = get_parity(operand);\n flags.S = 0;\n update_xy_flags(operand);\n \n return operand;\n};\n\nlet do_ix_add = function(operand)\n{\n flags.N = 0;\n \n var result = ix + operand;\n \n flags.C = (result & 0x10000) ? 1 : 0;\n flags.H = (((ix & 0xfff) + (operand & 0xfff)) & 0x1000) ? 1 : 0;\n update_xy_flags((result & 0xff00) >>> 8);\n \n ix = result & 0xffff;\n};\n\n\n///////////////////////////////////////////////////////////////////////////////\n/// This table contains the implementations for the instructions that weren't\n/// implemented directly in the decoder function (everything but the 8-bit\n/// register loads and the accumulator ALU instructions, in other words).\n/// Similar tables for the ED and DD/FD prefixes follow this one.\n///////////////////////////////////////////////////////////////////////////////\nlet instructions = [];\n\n// 0x00 : NOP\ninstructions[0x00] = function() { };\n// 0x01 : LD BC, nn\ninstructions[0x01] = function()\n{\n pc = (pc + 1) & 0xffff;\n c = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n b = core.mem_read(pc);\n};\n// 0x02 : LD (BC), A\ninstructions[0x02] = function()\n{\n core.mem_write(c | (b << 8), a);\n};\n// 0x03 : INC BC\ninstructions[0x03] = function()\n{\n var result = (c | (b << 8));\n result += 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n};\n// 0x04 : INC B\ninstructions[0x04] = function()\n{\n b = do_inc(b);\n};\n// 0x05 : DEC B\ninstructions[0x05] = function()\n{\n b = do_dec(b);\n};\n// 0x06 : LD B, n\ninstructions[0x06] = function()\n{\n pc = (pc + 1) & 0xffff;\n b = core.mem_read(pc);\n};\n// 0x07 : RLCA\ninstructions[0x07] = function()\n{\n // This instruction is implemented as a special case of the\n // more general Z80-specific RLC instruction.\n // Specifially, RLCA is a version of RLC A that affects fewer flags.\n // The same applies to RRCA, RLA, and RRA.\n var temp_s = flags.S, temp_z = flags.Z, temp_p = flags.P;\n a = do_rlc(a);\n flags.S = temp_s;\n flags.Z = temp_z;\n flags.P = temp_p;\n};\n// 0x08 : EX AF, AF'\ninstructions[0x08] = function()\n{\n var temp = a;\n a = a_prime;\n a_prime = temp;\n \n temp = get_flags_register();\n set_flags_register(get_flags_prime());\n set_flags_prime(temp);\n};\n// 0x09 : ADD HL, BC\ninstructions[0x09] = function()\n{\n do_hl_add(c | (b << 8));\n};\n// 0x0a : LD A, (BC)\ninstructions[0x0a] = function()\n{\n a = core.mem_read(c | (b << 8));\n};\n// 0x0b : DEC BC\ninstructions[0x0b] = function()\n{\n var result = (c | (b << 8));\n result -= 1;\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n};\n// 0x0c : INC C\ninstructions[0x0c] = function()\n{\n c = do_inc(c);\n};\n// 0x0d : DEC C\ninstructions[0x0d] = function()\n{\n c = do_dec(c);\n};\n// 0x0e : LD C, n\ninstructions[0x0e] = function()\n{\n pc = (pc + 1) & 0xffff;\n c = core.mem_read(pc);\n};\n// 0x0f : RRCA\ninstructions[0x0f] = function()\n{\n var temp_s = flags.S, temp_z = flags.Z, temp_p = flags.P;\n a = do_rrc(a);\n flags.S = temp_s;\n flags.Z = temp_z;\n flags.P = temp_p;\n};\n// 0x10 : DJNZ nn\ninstructions[0x10] = function()\n{\n b = (b - 1) & 0xff;\n do_conditional_relative_jump(b !== 0);\n};\n// 0x11 : LD DE, nn\ninstructions[0x11] = function()\n{\n pc = (pc + 1) & 0xffff;\n e = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n d = core.mem_read(pc);\n};\n// 0x12 : LD (DE), A\ninstructions[0x12] = function()\n{\n core.mem_write(e | (d << 8), a);\n};\n// 0x13 : INC DE\ninstructions[0x13] = function()\n{\n var result = (e | (d << 8));\n result += 1;\n e = result & 0xff;\n d = (result & 0xff00) >>> 8;\n};\n// 0x14 : INC D\ninstructions[0x14] = function()\n{\n d = do_inc(d);\n};\n// 0x15 : DEC D\ninstructions[0x15] = function()\n{\n d = do_dec(d);\n};\n// 0x16 : LD D, n\ninstructions[0x16] = function()\n{\n pc = (pc + 1) & 0xffff;\n d = core.mem_read(pc);\n};\n// 0x17 : RLA\ninstructions[0x17] = function()\n{\n var temp_s = flags.S, temp_z = flags.Z, temp_p = flags.P;\n a = do_rl(a);\n flags.S = temp_s;\n flags.Z = temp_z;\n flags.P = temp_p;\n};\n// 0x18 : JR n\ninstructions[0x18] = function()\n{\n var offset = get_signed_offset_byte(core.mem_read((pc + 1) & 0xffff));\n pc = (pc + offset + 1) & 0xffff;\n};\n// 0x19 : ADD HL, DE\ninstructions[0x19] = function()\n{\n do_hl_add(e | (d << 8));\n};\n// 0x1a : LD A, (DE)\ninstructions[0x1a] = function()\n{\n a = core.mem_read(e | (d << 8));\n};\n// 0x1b : DEC DE\ninstructions[0x1b] = function()\n{\n var result = (e | (d << 8));\n result -= 1;\n e = result & 0xff;\n d = (result & 0xff00) >>> 8;\n};\n// 0x1c : INC E\ninstructions[0x1c] = function()\n{\n e = do_inc(e);\n};\n// 0x1d : DEC E\ninstructions[0x1d] = function()\n{\n e = do_dec(e);\n};\n// 0x1e : LD E, n\ninstructions[0x1e] = function()\n{\n pc = (pc + 1) & 0xffff;\n e = core.mem_read(pc);\n};\n// 0x1f : RRA\ninstructions[0x1f] = function()\n{\n var temp_s = flags.S, temp_z = flags.Z, temp_p = flags.P;\n a = do_rr(a);\n flags.S = temp_s;\n flags.Z = temp_z;\n flags.P = temp_p;\n};\n// 0x20 : JR NZ, n\ninstructions[0x20] = function()\n{\n do_conditional_relative_jump(!flags.Z);\n};\n// 0x21 : LD HL, nn\ninstructions[0x21] = function()\n{\n pc = (pc + 1) & 0xffff;\n l = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n h = core.mem_read(pc);\n};\n// 0x22 : LD (nn), HL\ninstructions[0x22] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, l);\n core.mem_write((address + 1) & 0xffff, h);\n};\n// 0x23 : INC HL\ninstructions[0x23] = function()\n{\n var result = (l | (h << 8));\n result += 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n};\n// 0x24 : INC H\ninstructions[0x24] = function()\n{\n h = do_inc(h);\n};\n// 0x25 : DEC H\ninstructions[0x25] = function()\n{\n h = do_dec(h);\n};\n// 0x26 : LD H, n\ninstructions[0x26] = function()\n{\n pc = (pc + 1) & 0xffff;\n h = core.mem_read(pc);\n};\n// 0x27 : DAA\ninstructions[0x27] = function()\n{\n var temp = a;\n if (!flags.N)\n {\n if (flags.H || ((a & 0x0f) > 9))\n temp += 0x06;\n if (flags.C || (a > 0x99))\n temp += 0x60;\n }\n else\n {\n if (flags.H || ((a & 0x0f) > 9))\n temp -= 0x06;\n if (flags.C || (a > 0x99))\n temp -= 0x60;\n }\n \n flags.S = (temp & 0x80) ? 1 : 0;\n flags.Z = !(temp & 0xff) ? 1 : 0;\n flags.H = ((a & 0x10) ^ (temp & 0x10)) ? 1 : 0;\n flags.P = get_parity(temp & 0xff);\n // DAA never clears the carry flag if it was already set,\n // but it is able to set the carry flag if it was clear.\n // Don't ask me, I don't know.\n // Note also that we check for a BCD carry, instead of the usual.\n flags.C = (flags.C || (a > 0x99)) ? 1 : 0;\n \n a = temp & 0xff;\n \n update_xy_flags(a);\n};\n// 0x28 : JR Z, n\ninstructions[0x28] = function()\n{\n do_conditional_relative_jump(!!flags.Z);\n};\n// 0x29 : ADD HL, HL\ninstructions[0x29] = function()\n{\n do_hl_add(l | (h << 8));\n};\n// 0x2a : LD HL, (nn)\ninstructions[0x2a] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n l = core.mem_read(address);\n h = core.mem_read((address + 1) & 0xffff);\n};\n// 0x2b : DEC HL\ninstructions[0x2b] = function()\n{\n var result = (l | (h << 8));\n result -= 1;\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n};\n// 0x2c : INC L\ninstructions[0x2c] = function()\n{\n l = do_inc(l);\n};\n// 0x2d : DEC L\ninstructions[0x2d] = function()\n{\n l = do_dec(l);\n};\n// 0x2e : LD L, n\ninstructions[0x2e] = function()\n{\n pc = (pc + 1) & 0xffff;\n l = core.mem_read(pc);\n};\n// 0x2f : CPL\ninstructions[0x2f] = function()\n{\n a = (~a) & 0xff;\n flags.N = 1;\n flags.H = 1;\n update_xy_flags(a);\n};\n// 0x30 : JR NC, n\ninstructions[0x30] = function()\n{\n do_conditional_relative_jump(!flags.C);\n};\n// 0x31 : LD SP, nn\ninstructions[0x31] = function()\n{\n sp = core.mem_read((pc + 1) & 0xffff) | \n (core.mem_read((pc + 2) & 0xffff) << 8);\n pc = (pc + 2) & 0xffff;\n};\n// 0x32 : LD (nn), A\ninstructions[0x32] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, a);\n};\n// 0x33 : INC SP\ninstructions[0x33] = function()\n{\n sp = (sp + 1) & 0xffff;\n};\n// 0x34 : INC (HL)\ninstructions[0x34] = function()\n{\n var address = l | (h << 8);\n core.mem_write(address, do_inc(core.mem_read(address)));\n};\n// 0x35 : DEC (HL)\ninstructions[0x35] = function()\n{\n var address = l | (h << 8);\n core.mem_write(address, do_dec(core.mem_read(address)));\n};\n// 0x36 : LD (HL), n\ninstructions[0x36] = function()\n{\n pc = (pc + 1) & 0xffff;\n core.mem_write(l | (h << 8), core.mem_read(pc));\n};\n// 0x37 : SCF\ninstructions[0x37] = function()\n{\n flags.N = 0;\n flags.H = 0;\n flags.C = 1;\n update_xy_flags(a);\n};\n// 0x38 : JR C, n\ninstructions[0x38] = function()\n{\n do_conditional_relative_jump(!!flags.C);\n};\n// 0x39 : ADD HL, SP\ninstructions[0x39] = function()\n{\n do_hl_add(sp);\n};\n// 0x3a : LD A, (nn)\ninstructions[0x3a] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n a = core.mem_read(address);\n};\n// 0x3b : DEC SP\ninstructions[0x3b] = function()\n{\n sp = (sp - 1) & 0xffff;\n};\n// 0x3c : INC A\ninstructions[0x3c] = function()\n{\n a = do_inc(a);\n};\n// 0x3d : DEC A\ninstructions[0x3d] = function()\n{\n a = do_dec(a);\n};\n// 0x3e : LD A, n\ninstructions[0x3e] = function()\n{\n a = core.mem_read((pc + 1) & 0xffff);\n pc = (pc + 1) & 0xffff;\n};\n// 0x3f : CCF\ninstructions[0x3f] = function()\n{\n flags.N = 0;\n flags.H = flags.C;\n flags.C = flags.C ? 0 : 1;\n update_xy_flags(a);\n};\n// 0xc0 : RET NZ\ninstructions[0xc0] = function()\n{\n do_conditional_return(!flags.Z);\n};\n// 0xc1 : POP BC\ninstructions[0xc1] = function()\n{\n var result = pop_word();\n c = result & 0xff;\n b = (result & 0xff00) >>> 8;\n};\n// 0xc2 : JP NZ, nn\ninstructions[0xc2] = function()\n{\n do_conditional_absolute_jump(!flags.Z);\n};\n// 0xc3 : JP nn\ninstructions[0xc3] = function()\n{\n pc = core.mem_read((pc + 1) & 0xffff) |\n (core.mem_read((pc + 2) & 0xffff) << 8);\n pc = (pc - 1) & 0xffff;\n};\n// 0xc4 : CALL NZ, nn\ninstructions[0xc4] = function()\n{\n do_conditional_call(!flags.Z);\n};\n// 0xc5 : PUSH BC\ninstructions[0xc5] = function()\n{\n push_word(c | (b << 8));\n};\n// 0xc6 : ADD A, n\ninstructions[0xc6] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_add(core.mem_read(pc));\n};\n// 0xc7 : RST 00h\ninstructions[0xc7] = function()\n{\n do_reset(0x00);\n};\n// 0xc8 : RET Z\ninstructions[0xc8] = function()\n{\n do_conditional_return(!!flags.Z);\n};\n// 0xc9 : RET\ninstructions[0xc9] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n};\n// 0xca : JP Z, nn\ninstructions[0xca] = function()\n{\n do_conditional_absolute_jump(!!flags.Z);\n};\n// 0xcb : CB Prefix\ninstructions[0xcb] = function()\n{\n // R is incremented at the start of the second instruction cycle,\n // before the instruction actually runs.\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n\n // We don't have a table for this prefix,\n // the instructions are all so uniform that we can directly decode them.\n pc = (pc + 1) & 0xffff;\n var opcode = core.mem_read(pc),\n bit_number = (opcode & 0x38) >>> 3,\n reg_code = opcode & 0x07;\n \n if (opcode < 0x40)\n {\n // Shift/rotate instructions\n var op_array = [do_rlc, do_rrc, do_rl, do_rr,\n do_sla, do_sra, do_sll, do_srl];\n \n if (reg_code === 0)\n b = op_array[bit_number]( b);\n else if (reg_code === 1)\n c = op_array[bit_number]( c);\n else if (reg_code === 2)\n d = op_array[bit_number]( d);\n else if (reg_code === 3)\n e = op_array[bit_number]( e);\n else if (reg_code === 4)\n h = op_array[bit_number]( h);\n else if (reg_code === 5)\n l = op_array[bit_number]( l);\n else if (reg_code === 6)\n core.mem_write(l | (h << 8),\n op_array[bit_number]( core.mem_read(l | (h << 8))));\n else if (reg_code === 7)\n a = op_array[bit_number]( a);\n }\n else if (opcode < 0x80)\n {\n // BIT instructions\n if (reg_code === 0)\n flags.Z = !(b & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 1)\n flags.Z = !(c & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 2)\n flags.Z = !(d & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 3)\n flags.Z = !(e & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 4)\n flags.Z = !(h & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 5)\n flags.Z = !(l & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 6)\n flags.Z = !((core.mem_read(l | (h << 8))) & (1 << bit_number)) ? 1 : 0;\n else if (reg_code === 7)\n flags.Z = !(a & (1 << bit_number)) ? 1 : 0;\n \n flags.N = 0;\n flags.H = 1;\n flags.P = flags.Z;\n flags.S = ((bit_number === 7) && !flags.Z) ? 1 : 0;\n // For the BIT n, (HL) instruction, the X and Y flags are obtained\n // from what is apparently an internal temporary register used for\n // some of the 16-bit arithmetic instructions.\n // I haven't implemented that register here,\n // so for now we'll set X and Y the same way for every BIT opcode,\n // which means that they will usually be wrong for BIT n, (HL).\n flags.Y = ((bit_number === 5) && !flags.Z) ? 1 : 0;\n flags.X = ((bit_number === 3) && !flags.Z) ? 1 : 0;\n }\n else if (opcode < 0xc0)\n {\n // RES instructions\n if (reg_code === 0)\n b &= (0xff & ~(1 << bit_number));\n else if (reg_code === 1)\n c &= (0xff & ~(1 << bit_number));\n else if (reg_code === 2)\n d &= (0xff & ~(1 << bit_number));\n else if (reg_code === 3)\n e &= (0xff & ~(1 << bit_number));\n else if (reg_code === 4)\n h &= (0xff & ~(1 << bit_number));\n else if (reg_code === 5)\n l &= (0xff & ~(1 << bit_number));\n else if (reg_code === 6)\n core.mem_write(l | (h << 8),\n core.mem_read(l | (h << 8)) & ~(1 << bit_number));\n else if (reg_code === 7)\n a &= (0xff & ~(1 << bit_number));\n }\n else\n {\n // SET instructions\n if (reg_code === 0)\n b |= (1 << bit_number);\n else if (reg_code === 1)\n c |= (1 << bit_number);\n else if (reg_code === 2)\n d |= (1 << bit_number);\n else if (reg_code === 3)\n e |= (1 << bit_number);\n else if (reg_code === 4)\n h |= (1 << bit_number);\n else if (reg_code === 5)\n l |= (1 << bit_number);\n else if (reg_code === 6)\n core.mem_write(l | (h << 8),\n core.mem_read(l | (h << 8)) | (1 << bit_number));\n else if (reg_code === 7)\n a |= (1 << bit_number);\n }\n \n cycle_counter += cycle_counts_cb[opcode];\n};\n// 0xcc : CALL Z, nn\ninstructions[0xcc] = function()\n{\n do_conditional_call(!!flags.Z);\n};\n// 0xcd : CALL nn\ninstructions[0xcd] = function()\n{\n push_word((pc + 3) & 0xffff);\n pc = core.mem_read((pc + 1) & 0xffff) |\n (core.mem_read((pc + 2) & 0xffff) << 8);\n pc = (pc - 1) & 0xffff;\n};\n// 0xce : ADC A, n\ninstructions[0xce] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_adc(core.mem_read(pc));\n};\n// 0xcf : RST 08h\ninstructions[0xcf] = function()\n{\n do_reset(0x08);\n};\n// 0xd0 : RET NC\ninstructions[0xd0] = function()\n{\n do_conditional_return(!flags.C);\n};\n// 0xd1 : POP DE\ninstructions[0xd1] = function()\n{\n var result = pop_word();\n e = result & 0xff;\n d = (result & 0xff00) >>> 8;\n};\n// 0xd2 : JP NC, nn\ninstructions[0xd2] = function()\n{\n do_conditional_absolute_jump(!flags.C);\n};\n// 0xd3 : OUT (n), A\ninstructions[0xd3] = function()\n{\n pc = (pc + 1) & 0xffff;\n core.io_write((a << 8) | core.mem_read(pc), a);\n};\n// 0xd4 : CALL NC, nn\ninstructions[0xd4] = function()\n{\n do_conditional_call(!flags.C);\n};\n// 0xd5 : PUSH DE\ninstructions[0xd5] = function()\n{\n push_word(e | (d << 8));\n};\n// 0xd6 : SUB n\ninstructions[0xd6] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_sub(core.mem_read(pc));\n};\n// 0xd7 : RST 10h\ninstructions[0xd7] = function()\n{\n do_reset(0x10);\n};\n// 0xd8 : RET C\ninstructions[0xd8] = function()\n{\n do_conditional_return(!!flags.C);\n};\n// 0xd9 : EXX\ninstructions[0xd9] = function()\n{\n var temp = b;\n b = b_prime;\n b_prime = temp;\n temp = c;\n c = c_prime;\n c_prime = temp;\n temp = d;\n d = d_prime;\n d_prime = temp;\n temp = e;\n e = e_prime;\n e_prime = temp;\n temp = h;\n h = h_prime;\n h_prime = temp;\n temp = l;\n l = l_prime;\n l_prime = temp;\n};\n// 0xda : JP C, nn\ninstructions[0xda] = function()\n{\n do_conditional_absolute_jump(!!flags.C);\n};\n// 0xdb : IN A, (n)\ninstructions[0xdb] = function()\n{\n pc = (pc + 1) & 0xffff;\n a = core.io_read((a << 8) | core.mem_read(pc));\n};\n// 0xdc : CALL C, nn\ninstructions[0xdc] = function()\n{\n do_conditional_call(!!flags.C);\n};\n// 0xdd : DD Prefix (IX instructions)\ninstructions[0xdd] = function()\n{\n // R is incremented at the start of the second instruction cycle,\n // before the instruction actually runs.\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n\n pc = (pc + 1) & 0xffff;\n var opcode = core.mem_read(pc),\n func = dd_instructions[opcode];\n \n if (func)\n {\n //func = func.bind(this);\n func();\n cycle_counter += cycle_counts_dd[opcode];\n }\n else\n {\n // Apparently if a DD opcode doesn't exist,\n // it gets treated as an unprefixed opcode.\n // What we'll do to handle that is just back up the \n // program counter, so that this byte gets decoded\n // as a normal instruction.\n pc = (pc - 1) & 0xffff;\n // And we'll add in the cycle count for a NOP.\n cycle_counter += cycle_counts[0];\n }\n};\n// 0xde : SBC n\ninstructions[0xde] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_sbc(core.mem_read(pc));\n};\n// 0xdf : RST 18h\ninstructions[0xdf] = function()\n{\n do_reset(0x18);\n};\n// 0xe0 : RET PO\ninstructions[0xe0] = function()\n{\n do_conditional_return(!flags.P);\n};\n// 0xe1 : POP HL\ninstructions[0xe1] = function()\n{\n var result = pop_word();\n l = result & 0xff;\n h = (result & 0xff00) >>> 8;\n};\n// 0xe2 : JP PO, (nn)\ninstructions[0xe2] = function()\n{\n do_conditional_absolute_jump(!flags.P);\n};\n// 0xe3 : EX (SP), HL\ninstructions[0xe3] = function()\n{\n var temp = core.mem_read(sp);\n core.mem_write(sp, l);\n l = temp;\n temp = core.mem_read((sp + 1) & 0xffff);\n core.mem_write((sp + 1) & 0xffff, h);\n h = temp;\n};\n// 0xe4 : CALL PO, nn\ninstructions[0xe4] = function()\n{\n do_conditional_call(!flags.P);\n};\n// 0xe5 : PUSH HL\ninstructions[0xe5] = function()\n{\n push_word(l | (h << 8));\n};\n// 0xe6 : AND n\ninstructions[0xe6] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_and(core.mem_read(pc));\n};\n// 0xe7 : RST 20h\ninstructions[0xe7] = function()\n{\n do_reset(0x20);\n};\n// 0xe8 : RET PE\ninstructions[0xe8] = function()\n{\n do_conditional_return(!!flags.P);\n};\n// 0xe9 : JP (HL)\ninstructions[0xe9] = function()\n{\n pc = l | (h << 8);\n pc = (pc - 1) & 0xffff;\n};\n// 0xea : JP PE, nn\ninstructions[0xea] = function()\n{\n do_conditional_absolute_jump(!!flags.P);\n};\n// 0xeb : EX DE, HL\ninstructions[0xeb] = function()\n{\n var temp = d;\n d = h;\n h = temp;\n temp = e;\n e = l;\n l = temp;\n};\n// 0xec : CALL PE, nn\ninstructions[0xec] = function()\n{\n do_conditional_call(!!flags.P);\n};\n// 0xed : ED Prefix\ninstructions[0xed] = function()\n{\n // R is incremented at the start of the second instruction cycle,\n // before the instruction actually runs.\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n\n pc = (pc + 1) & 0xffff;\n var opcode = core.mem_read(pc),\n func = ed_instructions[opcode];\n \n if (func)\n {\n //func = func.bind(this);\n func();\n cycle_counter += cycle_counts_ed[opcode];\n }\n else\n {\n // If the opcode didn't exist, the whole thing is a two-byte NOP.\n cycle_counter += cycle_counts[0];\n }\n};\n// 0xee : XOR n\ninstructions[0xee] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_xor(core.mem_read(pc));\n};\n// 0xef : RST 28h\ninstructions[0xef] = function()\n{\n do_reset(0x28);\n};\n// 0xf0 : RET P\ninstructions[0xf0] = function()\n{\n do_conditional_return(!flags.S);\n};\n// 0xf1 : POP AF\ninstructions[0xf1] = function()\n{\n var result = pop_word();\n set_flags_register(result & 0xff);\n a = (result & 0xff00) >>> 8;\n};\n// 0xf2 : JP P, nn\ninstructions[0xf2] = function()\n{\n do_conditional_absolute_jump(!flags.S);\n};\n// 0xf3 : DI\ninstructions[0xf3] = function()\n{\n // DI doesn't actually take effect until after the next instruction.\n do_delayed_di = true;\n};\n// 0xf4 : CALL P, nn\ninstructions[0xf4] = function()\n{\n do_conditional_call(!flags.S);\n};\n// 0xf5 : PUSH AF\ninstructions[0xf5] = function()\n{\n push_word(get_flags_register() | (a << 8));\n};\n// 0xf6 : OR n\ninstructions[0xf6] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_or(core.mem_read(pc));\n};\n// 0xf7 : RST 30h\ninstructions[0xf7] = function()\n{\n do_reset(0x30);\n};\n// 0xf8 : RET M\ninstructions[0xf8] = function()\n{\n do_conditional_return(!!flags.S);\n};\n// 0xf9 : LD SP, HL\ninstructions[0xf9] = function()\n{\n sp = l | (h << 8);\n};\n// 0xfa : JP M, nn\ninstructions[0xfa] = function()\n{\n do_conditional_absolute_jump(!!flags.S);\n};\n// 0xfb : EI\ninstructions[0xfb] = function()\n{\n // EI doesn't actually take effect until after the next instruction.\n do_delayed_ei = true;\n};\n// 0xfc : CALL M, nn\ninstructions[0xfc] = function()\n{\n do_conditional_call(!!flags.S);\n};\n// 0xfd : FD Prefix (IY instructions)\ninstructions[0xfd] = function()\n{\n // R is incremented at the start of the second instruction cycle,\n // before the instruction actually runs.\n // The high bit of R is not affected by this increment,\n // it can only be changed using the LD R, A instruction.\n r = (r & 0x80) | (((r & 0x7f) + 1) & 0x7f);\n \n pc = (pc + 1) & 0xffff;\n var opcode = core.mem_read(pc),\n func = dd_instructions[opcode];\n \n if (func)\n {\n // Rather than copy and paste all the IX instructions into IY instructions,\n // what we'll do is sneakily copy IY into IX, run the IX instruction,\n // and then copy the result into IY and restore the old IX.\n var temp = ix;\n ix = iy;\n //func = func.bind(this);\n func();\n iy = ix;\n ix = temp;\n \n cycle_counter += cycle_counts_dd[opcode];\n }\n else\n {\n // Apparently if an FD opcode doesn't exist,\n // it gets treated as an unprefixed opcode.\n // What we'll do to handle that is just back up the \n // program counter, so that this byte gets decoded\n // as a normal instruction.\n pc = (pc - 1) & 0xffff;\n // And we'll add in the cycle count for a NOP.\n cycle_counter += cycle_counts[0];\n }\n};\n// 0xfe : CP n\ninstructions[0xfe] = function()\n{\n pc = (pc + 1) & 0xffff;\n do_cp(core.mem_read(pc));\n};\n// 0xff : RST 38h\ninstructions[0xff] = function()\n{\n do_reset(0x38);\n};\n\n\n///////////////////////////////////////////////////////////////////////////////\n/// This table of ED opcodes is pretty sparse;\n/// there are not very many valid ED-prefixed opcodes in the Z80,\n/// and many of the ones that are valid are not documented.\n///////////////////////////////////////////////////////////////////////////////\nlet ed_instructions = [];\n// 0x40 : IN B, (C)\ned_instructions[0x40] = function()\n{\n b = do_in((b << 8) | c);\n};\n// 0x41 : OUT (C), B\ned_instructions[0x41] = function()\n{\n core.io_write((b << 8) | c, b);\n};\n// 0x42 : SBC HL, BC\ned_instructions[0x42] = function()\n{\n do_hl_sbc(c | (b << 8));\n};\n// 0x43 : LD (nn), BC\ned_instructions[0x43] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, c);\n core.mem_write((address + 1) & 0xffff, b);\n};\n// 0x44 : NEG\ned_instructions[0x44] = function()\n{\n do_neg();\n};\n// 0x45 : RETN\ned_instructions[0x45] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x46 : IM 0\ned_instructions[0x46] = function()\n{\n imode = 0;\n};\n// 0x47 : LD I, A\ned_instructions[0x47] = function()\n{\n i = a\n};\n// 0x48 : IN C, (C)\ned_instructions[0x48] = function()\n{\n c = do_in((b << 8) | c);\n};\n// 0x49 : OUT (C), C\ned_instructions[0x49] = function()\n{\n core.io_write((b << 8) | c, c);\n};\n// 0x4a : ADC HL, BC\ned_instructions[0x4a] = function()\n{\n do_hl_adc(c | (b << 8));\n};\n// 0x4b : LD BC, (nn)\ned_instructions[0x4b] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n c = core.mem_read(address);\n b = core.mem_read((address + 1) & 0xffff);\n};\n// 0x4c : NEG (Undocumented)\ned_instructions[0x4c] = function()\n{\n do_neg();\n};\n// 0x4d : RETI\ned_instructions[0x4d] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n};\n// 0x4e : IM 0 (Undocumented)\ned_instructions[0x4e] = function()\n{\n imode = 0;\n};\n// 0x4f : LD R, A\ned_instructions[0x4f] = function()\n{\n r = a;\n};\n// 0x50 : IN D, (C)\ned_instructions[0x50] = function()\n{\n d = do_in((b << 8) | c);\n};\n// 0x51 : OUT (C), D\ned_instructions[0x51] = function()\n{\n core.io_write((b << 8) | c, d);\n};\n// 0x52 : SBC HL, DE\ned_instructions[0x52] = function()\n{\n do_hl_sbc(e | (d << 8));\n};\n// 0x53 : LD (nn), DE\ned_instructions[0x53] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, e);\n core.mem_write((address + 1) & 0xffff, d);\n};\n// 0x54 : NEG (Undocumented)\ned_instructions[0x54] = function()\n{\n do_neg();\n};\n// 0x55 : RETN\ned_instructions[0x55] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x56 : IM 1\ned_instructions[0x56] = function()\n{\n imode = 1;\n};\n// 0x57 : LD A, I\ned_instructions[0x57] = function()\n{\n a = i;\n flags.S = a & 0x80 ? 1 : 0;\n flags.Z = a ? 0 : 1;\n flags.H = 0;\n flags.P = iff2;\n flags.N = 0;\n update_xy_flags(a);\n};\n// 0x58 : IN E, (C)\ned_instructions[0x58] = function()\n{\n e = do_in((b << 8) | c);\n};\n// 0x59 : OUT (C), E\ned_instructions[0x59] = function()\n{\n core.io_write((b << 8) | c, e);\n};\n// 0x5a : ADC HL, DE\ned_instructions[0x5a] = function()\n{\n do_hl_adc(e | (d << 8));\n};\n// 0x5b : LD DE, (nn)\ned_instructions[0x5b] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n e = core.mem_read(address);\n d = core.mem_read((address + 1) & 0xffff);\n};\n// 0x5c : NEG (Undocumented)\ned_instructions[0x5c] = function()\n{\n do_neg();\n};\n// 0x5d : RETN\ned_instructions[0x5d] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x5e : IM 2\ned_instructions[0x5e] = function()\n{\n imode = 2;\n};\n// 0x5f : LD A, R\ned_instructions[0x5f] = function()\n{\n a = r;\n flags.S = a & 0x80 ? 1 : 0;\n flags.Z = a ? 0 : 1;\n flags.H = 0;\n flags.P = iff2;\n flags.N = 0;\n update_xy_flags(a);\n};\n// 0x60 : IN H, (C)\ned_instructions[0x60] = function()\n{\n h = do_in((b << 8) | c);\n};\n// 0x61 : OUT (C), H\ned_instructions[0x61] = function()\n{\n core.io_write((b << 8) | c, h);\n};\n// 0x62 : SBC HL, HL\ned_instructions[0x62] = function()\n{\n do_hl_sbc(l | (h << 8));\n};\n// 0x63 : LD (nn), HL (Undocumented)\ned_instructions[0x63] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, l);\n core.mem_write((address + 1) & 0xffff, h);\n};\n// 0x64 : NEG (Undocumented)\ned_instructions[0x64] = function()\n{\n do_neg();\n};\n// 0x65 : RETN\ned_instructions[0x65] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x66 : IM 0\ned_instructions[0x66] = function()\n{\n imode = 0;\n};\n// 0x67 : RRD\ned_instructions[0x67] = function()\n{\n var hl_value = core.mem_read(l | (h << 8));\n var temp1 = hl_value & 0x0f, temp2 = a & 0x0f;\n hl_value = ((hl_value & 0xf0) >>> 4) | (temp2 << 4);\n a = (a & 0xf0) | temp1;\n core.mem_write(l | (h << 8), hl_value);\n \n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = a ? 0 : 1;\n flags.H = 0;\n flags.P = get_parity(a) ? 1 : 0;\n flags.N = 0;\n update_xy_flags(a);\n};\n// 0x68 : IN L, (C)\ned_instructions[0x68] = function()\n{\n l = do_in((b << 8) | c);\n};\n// 0x69 : OUT (C), L\ned_instructions[0x69] = function()\n{\n core.io_write((b << 8) | c, l);\n};\n// 0x6a : ADC HL, HL\ned_instructions[0x6a] = function()\n{\n do_hl_adc(l | (h << 8));\n};\n// 0x6b : LD HL, (nn) (Undocumented)\ned_instructions[0x6b] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n l = core.mem_read(address);\n h = core.mem_read((address + 1) & 0xffff);\n};\n// 0x6c : NEG (Undocumented)\ned_instructions[0x6c] = function()\n{\n do_neg();\n};\n// 0x6d : RETN\ned_instructions[0x6d] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x6e : IM 0 (Undocumented)\ned_instructions[0x6e] = function()\n{\n imode = 0;\n};\n// 0x6f : RLD\ned_instructions[0x6f] = function()\n{\n var hl_value = core.mem_read(l | (h << 8));\n var temp1 = hl_value & 0xf0, temp2 = a & 0x0f;\n hl_value = ((hl_value & 0x0f) << 4) | temp2;\n a = (a & 0xf0) | (temp1 >>> 4);\n core.mem_write(l | (h << 8), hl_value);\n \n flags.S = (a & 0x80) ? 1 : 0;\n flags.Z = a ? 0 : 1;\n flags.H = 0;\n flags.P = get_parity(a) ? 1 : 0;\n flags.N = 0;\n update_xy_flags(a);\n};\n// 0x70 : IN (C) (Undocumented)\ned_instructions[0x70] = function()\n{\n do_in((b << 8) | c);\n};\n// 0x71 : OUT (C), 0 (Undocumented)\ned_instructions[0x71] = function()\n{\n core.io_write((b << 8) | c, 0);\n};\n// 0x72 : SBC HL, SP\ned_instructions[0x72] = function()\n{\n do_hl_sbc(sp);\n};\n// 0x73 : LD (nn), SP\ned_instructions[0x73] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n core.mem_write(address, sp & 0xff);\n core.mem_write((address + 1) & 0xffff, (sp >>> 8) & 0xff);\n};\n// 0x74 : NEG (Undocumented)\ned_instructions[0x74] = function()\n{\n do_neg();\n};\n// 0x75 : RETN\ned_instructions[0x75] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x76 : IM 1\ned_instructions[0x76] = function()\n{\n imode = 1;\n};\n// 0x78 : IN A, (C)\ned_instructions[0x78] = function()\n{\n a = do_in((b << 8) | c);\n};\n// 0x79 : OUT (C), A\ned_instructions[0x79] = function()\n{\n core.io_write((b << 8) | c, a);\n};\n// 0x7a : ADC HL, SP\ned_instructions[0x7a] = function()\n{\n do_hl_adc(sp);\n};\n// 0x7b : LD SP, (nn)\ned_instructions[0x7b] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= core.mem_read(pc) << 8;\n \n sp = core.mem_read(address);\n sp |= core.mem_read((address + 1) & 0xffff) << 8;\n};\n// 0x7c : NEG (Undocumented)\ned_instructions[0x7c] = function()\n{\n do_neg();\n};\n// 0x7d : RETN\ned_instructions[0x7d] = function()\n{\n pc = (pop_word() - 1) & 0xffff;\n iff1 = iff2;\n};\n// 0x7e : IM 2\ned_instructions[0x7e] = function()\n{\n imode = 2;\n};\n// 0xa0 : LDI\ned_instructions[0xa0] = function()\n{\n do_ldi();\n};\n// 0xa1 : CPI\ned_instructions[0xa1] = function()\n{\n do_cpi();\n};\n// 0xa2 : INI\ned_instructions[0xa2] = function()\n{\n do_ini();\n};\n// 0xa3 : OUTI\ned_instructions[0xa3] = function()\n{\n do_outi();\n};\n// 0xa8 : LDD\ned_instructions[0xa8] = function()\n{\n do_ldd();\n};\n// 0xa9 : CPD\ned_instructions[0xa9] = function()\n{\n do_cpd();\n};\n// 0xaa : IND\ned_instructions[0xaa] = function()\n{\n do_ind();\n};\n// 0xab : OUTD\ned_instructions[0xab] = function()\n{\n do_outd();\n};\n// 0xb0 : LDIR\ned_instructions[0xb0] = function()\n{\n do_ldi();\n if (b || c)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xb1 : CPIR\ned_instructions[0xb1] = function()\n{\n do_cpi();\n if (!flags.Z && (b || c))\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xb2 : INIR\ned_instructions[0xb2] = function()\n{\n do_ini();\n if (b)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xb3 : OTIR\ned_instructions[0xb3] = function()\n{\n do_outi();\n if (b)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xb8 : LDDR\ned_instructions[0xb8] = function()\n{\n do_ldd();\n if (b || c)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xb9 : CPDR\ned_instructions[0xb9] = function()\n{\n do_cpd();\n if (!flags.Z && (b || c))\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xba : INDR\ned_instructions[0xba] = function()\n{\n do_ind();\n if (b)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n// 0xbb : OTDR\ned_instructions[0xbb] = function()\n{\n do_outd();\n if (b)\n {\n cycle_counter += 5;\n pc = (pc - 2) & 0xffff;\n }\n};\n\n\n///////////////////////////////////////////////////////////////////////////////\n/// Like ED, this table is quite sparse,\n/// and many of the opcodes here are also undocumented.\n/// The undocumented instructions here are those that deal with only one byte\n/// of the two-byte IX register; the bytes are designed IXH and IXL here.\n///////////////////////////////////////////////////////////////////////////////\nlet dd_instructions = [];\n// 0x09 : ADD IX, BC\ndd_instructions[0x09] = function()\n{\n do_ix_add(c | (b << 8));\n};\n// 0x19 : ADD IX, DE\ndd_instructions[0x19] = function()\n{\n do_ix_add(e | (d << 8));\n};\n// 0x21 : LD IX, nn\ndd_instructions[0x21] = function()\n{\n pc = (pc + 1) & 0xffff;\n ix = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n ix |= (core.mem_read(pc) << 8);\n};\n// 0x22 : LD (nn), IX\ndd_instructions[0x22] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= (core.mem_read(pc) << 8);\n \n core.mem_write(address, ix & 0xff);\n core.mem_write((address + 1) & 0xffff, (ix >>> 8) & 0xff);\n};\n// 0x23 : INC IX\ndd_instructions[0x23] = function()\n{\n ix = (ix + 1) & 0xffff;\n};\n// 0x24 : INC IXH (Undocumented)\ndd_instructions[0x24] = function()\n{\n ix = (do_inc(ix >>> 8) << 8) | (ix & 0xff);\n};\n// 0x25 : DEC IXH (Undocumented)\ndd_instructions[0x25] = function()\n{\n ix = (do_dec(ix >>> 8) << 8) | (ix & 0xff);\n};\n// 0x26 : LD IXH, n (Undocumented)\ndd_instructions[0x26] = function()\n{\n pc = (pc + 1) & 0xffff;\n ix = (core.mem_read(pc) << 8) | (ix & 0xff);\n};\n// 0x29 : ADD IX, IX\ndd_instructions[0x29] = function()\n{\n do_ix_add(ix);\n};\n// 0x2a : LD IX, (nn)\ndd_instructions[0x2a] = function()\n{\n pc = (pc + 1) & 0xffff;\n var address = core.mem_read(pc);\n pc = (pc + 1) & 0xffff;\n address |= (core.mem_read(pc) << 8);\n \n ix = core.mem_read(address);\n ix |= (core.mem_read((address + 1) & 0xffff) << 8);\n};\n// 0x2b : DEC IX\ndd_instructions[0x2b] = function()\n{\n ix = (ix - 1) & 0xffff;\n};\n// 0x2c : INC IXL (Undocumented)\ndd_instructions[0x2c] = function()\n{\n ix = do_inc(ix & 0xff) | (ix & 0xff00);\n};\n// 0x2d : DEC IXL (Undocumented)\ndd_instructions[0x2d] = function()\n{\n ix = do_dec(ix & 0xff) | (ix & 0xff00);\n};\n// 0x2e : LD IXL, n (Undocumented)\ndd_instructions[0x2e] = function()\n{\n pc = (pc + 1) & 0xffff;\n ix = (core.mem_read(pc) & 0xff) | (ix & 0xff00);\n};\n// 0x34 : INC (IX+n)\ndd_instructions[0x34] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc)),\n value = core.mem_read((offset + ix) & 0xffff);\n core.mem_write((offset + ix) & 0xffff, do_inc(value));\n};\n// 0x35 : DEC (IX+n)\ndd_instructions[0x35] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc)),\n value = core.mem_read((offset + ix) & 0xffff);\n core.mem_write((offset + ix) & 0xffff, do_dec(value));\n};\n// 0x36 : LD (IX+n), n\ndd_instructions[0x36] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n pc = (pc + 1) & 0xffff;\n core.mem_write((ix + offset) & 0xffff, core.mem_read(pc)); \n};\n// 0x39 : ADD IX, SP\ndd_instructions[0x39] = function()\n{\n do_ix_add(sp);\n};\n// 0x44 : LD B, IXH (Undocumented)\ndd_instructions[0x44] = function()\n{\n b = (ix >>> 8) & 0xff;\n};\n// 0x45 : LD B, IXL (Undocumented)\ndd_instructions[0x45] = function()\n{\n b = ix & 0xff;\n};\n// 0x46 : LD B, (IX+n)\ndd_instructions[0x46] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n b = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x4c : LD C, IXH (Undocumented)\ndd_instructions[0x4c] = function()\n{\n c = (ix >>> 8) & 0xff;\n};\n// 0x4d : LD C, IXL (Undocumented)\ndd_instructions[0x4d] = function()\n{\n c = ix & 0xff;\n};\n// 0x4e : LD C, (IX+n)\ndd_instructions[0x4e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n c = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x54 : LD D, IXH (Undocumented)\ndd_instructions[0x54] = function()\n{\n d = (ix >>> 8) & 0xff;\n};\n// 0x55 : LD D, IXL (Undocumented)\ndd_instructions[0x55] = function()\n{\n d = ix & 0xff;\n};\n// 0x56 : LD D, (IX+n)\ndd_instructions[0x56] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n d = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x5c : LD E, IXH (Undocumented)\ndd_instructions[0x5c] = function()\n{\n e = (ix >>> 8) & 0xff;\n};\n// 0x5d : LD E, IXL (Undocumented)\ndd_instructions[0x5d] = function()\n{\n e = ix & 0xff;\n};\n// 0x5e : LD E, (IX+n)\ndd_instructions[0x5e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n e = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x60 : LD IXH, B (Undocumented)\ndd_instructions[0x60] = function()\n{\n ix = (ix & 0xff) | (b << 8);\n};\n// 0x61 : LD IXH, C (Undocumented)\ndd_instructions[0x61] = function()\n{\n ix = (ix & 0xff) | (c << 8);\n};\n// 0x62 : LD IXH, D (Undocumented)\ndd_instructions[0x62] = function()\n{\n ix = (ix & 0xff) | (d << 8);\n};\n// 0x63 : LD IXH, E (Undocumented)\ndd_instructions[0x63] = function()\n{\n ix = (ix & 0xff) | (e << 8);\n};\n// 0x64 : LD IXH, IXH (Undocumented)\ndd_instructions[0x64] = function()\n{\n // No-op.\n};\n// 0x65 : LD IXH, IXL (Undocumented)\ndd_instructions[0x65] = function()\n{\n ix = (ix & 0xff) | ((ix & 0xff) << 8);\n};\n// 0x66 : LD H, (IX+n)\ndd_instructions[0x66] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n h = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x67 : LD IXH, A (Undocumented)\ndd_instructions[0x67] = function()\n{\n ix = (ix & 0xff) | (a << 8);\n};\n// 0x68 : LD IXL, B (Undocumented)\ndd_instructions[0x68] = function()\n{\n ix = (ix & 0xff00) | b;\n};\n// 0x69 : LD IXL, C (Undocumented)\ndd_instructions[0x69] = function()\n{\n ix = (ix & 0xff00) | c;\n};\n// 0x6a : LD IXL, D (Undocumented)\ndd_instructions[0x6a] = function()\n{\n ix = (ix & 0xff00) | d;\n};\n// 0x6b : LD IXL, E (Undocumented)\ndd_instructions[0x6b] = function()\n{\n ix = (ix & 0xff00) | e;\n};\n// 0x6c : LD IXL, IXH (Undocumented)\ndd_instructions[0x6c] = function()\n{\n ix = (ix & 0xff00) | (ix >>> 8);\n};\n// 0x6d : LD IXL, IXL (Undocumented)\ndd_instructions[0x6d] = function()\n{\n // No-op.\n};\n// 0x6e : LD L, (IX+n)\ndd_instructions[0x6e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n l = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x6f : LD IXL, A (Undocumented)\ndd_instructions[0x6f] = function()\n{\n ix = (ix & 0xff00) | a;\n};\n// 0x70 : LD (IX+n), B\ndd_instructions[0x70] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, b);\n};\n// 0x71 : LD (IX+n), C\ndd_instructions[0x71] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, c);\n};\n// 0x72 : LD (IX+n), D\ndd_instructions[0x72] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, d);\n};\n// 0x73 : LD (IX+n), E\ndd_instructions[0x73] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, e);\n};\n// 0x74 : LD (IX+n), H\ndd_instructions[0x74] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, h);\n};\n// 0x75 : LD (IX+n), L\ndd_instructions[0x75] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, l);\n};\n// 0x77 : LD (IX+n), A\ndd_instructions[0x77] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n core.mem_write((ix + offset) & 0xffff, a);\n};\n// 0x7c : LD A, IXH (Undocumented)\ndd_instructions[0x7c] = function()\n{\n a = (ix >>> 8) & 0xff;\n};\n// 0x7d : LD A, IXL (Undocumented)\ndd_instructions[0x7d] = function()\n{\n a = ix & 0xff;\n};\n// 0x7e : LD A, (IX+n)\ndd_instructions[0x7e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n a = core.mem_read((ix + offset) & 0xffff);\n};\n// 0x84 : ADD A, IXH (Undocumented)\ndd_instructions[0x84] = function()\n{\n do_add((ix >>> 8) & 0xff);\n};\n// 0x85 : ADD A, IXL (Undocumented)\ndd_instructions[0x85] = function()\n{\n do_add(ix & 0xff);\n};\n// 0x86 : ADD A, (IX+n)\ndd_instructions[0x86] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_add(core.mem_read((ix + offset) & 0xffff));\n};\n// 0x8c : ADC A, IXH (Undocumented)\ndd_instructions[0x8c] = function()\n{\n do_adc((ix >>> 8) & 0xff);\n};\n// 0x8d : ADC A, IXL (Undocumented)\ndd_instructions[0x8d] = function()\n{\n do_adc(ix & 0xff);\n};\n// 0x8e : ADC A, (IX+n)\ndd_instructions[0x8e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_adc(core.mem_read((ix + offset) & 0xffff));\n};\n// 0x94 : SUB IXH (Undocumented)\ndd_instructions[0x94] = function()\n{\n do_sub((ix >>> 8) & 0xff);\n};\n// 0x95 : SUB IXL (Undocumented)\ndd_instructions[0x95] = function()\n{\n do_sub(ix & 0xff);\n};\n// 0x96 : SUB A, (IX+n)\ndd_instructions[0x96] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_sub(core.mem_read((ix + offset) & 0xffff));\n};\n// 0x9c : SBC IXH (Undocumented)\ndd_instructions[0x9c] = function()\n{\n do_sbc((ix >>> 8) & 0xff);\n};\n// 0x9d : SBC IXL (Undocumented)\ndd_instructions[0x9d] = function()\n{\n do_sbc(ix & 0xff);\n};\n// 0x9e : SBC A, (IX+n)\ndd_instructions[0x9e] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_sbc(core.mem_read((ix + offset) & 0xffff));\n};\n// 0xa4 : AND IXH (Undocumented)\ndd_instructions[0xa4] = function()\n{\n do_and((ix >>> 8) & 0xff);\n};\n// 0xa5 : AND IXL (Undocumented)\ndd_instructions[0xa5] = function()\n{\n do_and(ix & 0xff);\n};\n// 0xa6 : AND A, (IX+n)\ndd_instructions[0xa6] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_and(core.mem_read((ix + offset) & 0xffff));\n};\n// 0xac : XOR IXH (Undocumented)\ndd_instructions[0xac] = function()\n{\n do_xor((ix >>> 8) & 0xff);\n};\n// 0xad : XOR IXL (Undocumented)\ndd_instructions[0xad] = function()\n{\n do_xor(ix & 0xff);\n};\n// 0xae : XOR A, (IX+n)\ndd_instructions[0xae] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_xor(core.mem_read((ix + offset) & 0xffff));\n};\n// 0xb4 : OR IXH (Undocumented)\ndd_instructions[0xb4] = function()\n{\n do_or((ix >>> 8) & 0xff);\n};\n// 0xb5 : OR IXL (Undocumented)\ndd_instructions[0xb5] = function()\n{\n do_or(ix & 0xff);\n};\n// 0xb6 : OR A, (IX+n)\ndd_instructions[0xb6] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_or(core.mem_read((ix + offset) & 0xffff));\n};\n// 0xbc : CP IXH (Undocumented)\ndd_instructions[0xbc] = function()\n{\n do_cp((ix >>> 8) & 0xff);\n};\n// 0xbd : CP IXL (Undocumented)\ndd_instructions[0xbd] = function()\n{\n do_cp(ix & 0xff);\n};\n// 0xbe : CP A, (IX+n)\ndd_instructions[0xbe] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n do_cp(core.mem_read((ix + offset) & 0xffff));\n};\n// 0xcb : CB Prefix (IX bit instructions)\ndd_instructions[0xcb] = function()\n{\n pc = (pc + 1) & 0xffff;\n var offset = get_signed_offset_byte(core.mem_read(pc));\n pc = (pc + 1) & 0xffff;\n var opcode = core.mem_read(pc), value;\n \n // As with the \"normal\" CB prefix, we implement the DDCB prefix\n // by decoding the opcode directly, rather than using a table.\n if (opcode < 0x40)\n {\n // Shift and rotate instructions.\n var ddcb_functions = [do_rlc, do_rrc, do_rl, do_rr,\n do_sla, do_sra, do_sll, do_srl];\n \n // Most of the opcodes in this range are not valid,\n // so we map this opcode onto one of the ones that is.\n var func = ddcb_functions[(opcode & 0x38) >>> 3],\n value = func( core.mem_read((ix + offset) & 0xffff));\n \n core.mem_write((ix + offset) & 0xffff, value);\n }\n else\n {\n var bit_number = (opcode & 0x38) >>> 3;\n \n if (opcode < 0x80)\n {\n // BIT\n flags.N = 0;\n flags.H = 1;\n flags.Z = !(core.mem_read((ix + offset) & 0xffff) & (1 << bit_number)) ? 1 : 0;\n flags.P = flags.Z;\n flags.S = ((bit_number === 7) && !flags.Z) ? 1 : 0;\n }\n else if (opcode < 0xc0)\n {\n // RES\n value = core.mem_read((ix + offset) & 0xffff) & ~(1 << bit_number) & 0xff;\n core.mem_write((ix + offset) & 0xffff, value);\n }\n else\n {\n // SET\n value = core.mem_read((ix + offset) & 0xffff) | (1 << bit_number);\n core.mem_write((ix + offset) & 0xffff, value);\n }\n }\n \n // This implements the undocumented shift, RES, and SET opcodes,\n // which write their result to memory and also to an 8080 register.\n if (value !== undefined)\n {\n if ((opcode & 0x07) === 0)\n b = value;\n else if ((opcode & 0x07) === 1)\n c = value;\n else if ((opcode & 0x07) === 2)\n d = value;\n else if ((opcode & 0x07) === 3)\n e = value;\n else if ((opcode & 0x07) === 4)\n h = value;\n else if ((opcode & 0x07) === 5)\n l = value;\n // 6 is the documented opcode, which doesn't set a register.\n else if ((opcode & 0x07) === 7)\n a = value;\n }\n \n cycle_counter += cycle_counts_cb[opcode] + 8;\n};\n// 0xe1 : POP IX\ndd_instructions[0xe1] = function()\n{\n ix = pop_word();\n};\n// 0xe3 : EX (SP), IX\ndd_instructions[0xe3] = function()\n{\n var temp = ix;\n ix = core.mem_read(sp);\n ix |= core.mem_read((sp + 1) & 0xffff) << 8;\n core.mem_write(sp, temp & 0xff);\n core.mem_write((sp + 1) & 0xffff, (temp >>> 8) & 0xff);\n};\n// 0xe5 : PUSH IX\ndd_instructions[0xe5] = function()\n{\n push_word(ix);\n};\n// 0xe9 : JP (IX)\ndd_instructions[0xe9] = function()\n{\n pc = (ix - 1) & 0xffff;\n};\n// 0xf9 : LD SP, IX\ndd_instructions[0xf9] = function()\n{\n sp = ix;\n};\n\n\n///////////////////////////////////////////////////////////////////////////////\n/// These tables contain the number of T cycles used for each instruction.\n/// In a few special cases, such as conditional control flow instructions,\n/// additional cycles might be added to these values.\n/// The total number of cycles is the return value of run_instruction().\n///////////////////////////////////////////////////////////////////////////////\nlet cycle_counts = [\n 4, 10, 7, 6, 4, 4, 7, 4, 4, 11, 7, 6, 4, 4, 7, 4,\n 8, 10, 7, 6, 4, 4, 7, 4, 12, 11, 7, 6, 4, 4, 7, 4,\n 7, 10, 16, 6, 4, 4, 7, 4, 7, 11, 16, 6, 4, 4, 7, 4,\n 7, 10, 13, 6, 11, 11, 10, 4, 7, 11, 13, 6, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,\n 5, 10, 10, 10, 10, 11, 7, 11, 5, 10, 10, 0, 10, 17, 7, 11,\n 5, 10, 10, 11, 10, 11, 7, 11, 5, 4, 10, 11, 10, 0, 7, 11,\n 5, 10, 10, 19, 10, 11, 7, 11, 5, 4, 10, 4, 10, 0, 7, 11,\n 5, 10, 10, 4, 10, 11, 7, 11, 5, 6, 10, 4, 10, 0, 7, 11\n];\n\nlet cycle_counts_ed = [\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 12, 12, 15, 20, 8, 14, 8, 9, 12, 12, 15, 20, 8, 14, 8, 9,\n 12, 12, 15, 20, 8, 14, 8, 9, 12, 12, 15, 20, 8, 14, 8, 9,\n 12, 12, 15, 20, 8, 14, 8, 18, 12, 12, 15, 20, 8, 14, 8, 18,\n 12, 12, 15, 20, 8, 14, 8, 0, 12, 12, 15, 20, 8, 14, 8, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 16, 16, 16, 16, 0, 0, 0, 0, 16, 16, 16, 16, 0, 0, 0, 0,\n 16, 16, 16, 16, 0, 0, 0, 0, 16, 16, 16, 16, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\n];\n\nlet cycle_counts_cb = [\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 8, 12, 8,\n 8, 8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 8, 12, 8,\n 8, 8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 8, 12, 8,\n 8, 8, 8, 8, 8, 8, 12, 8, 8, 8, 8, 8, 8, 8, 12, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8,\n 8, 8, 8, 8, 8, 8, 15, 8, 8, 8, 8, 8, 8, 8, 15, 8\n];\n\nlet cycle_counts_dd = [\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0,\n 0, 14, 20, 10, 8, 8, 11, 0, 0, 15, 20, 10, 8, 8, 11, 0,\n 0, 0, 0, 0, 23, 23, 19, 0, 0, 15, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 8, 8, 8, 8, 8, 8, 19, 8, 8, 8, 8, 8, 8, 8, 19, 8,\n 19, 19, 19, 19, 19, 19, 0, 19, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 8, 8, 19, 0, 0, 0, 0, 0, 8, 8, 19, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 14, 0, 23, 0, 15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0\n];\n\n // There's tons of stuff in this object,\n // but only these three functions are the public API.\n this.saveState = getState;\n this.loadState = setState;\n this.reset = reset;\n this.advanceInsn = run_instruction;\n this.interrupt = interrupt;\n this.getPC = ():number => { return pc; }\n this.getSP = ():number => { return sp; }\n this.getHalted = ():boolean => { return halted; }\n}\n\nexport interface Z80State {\nAF : number;\nBC : number;\nDE : number;\nHL : number;\nAF_ : number;\nBC_ : number;\nDE_ : number;\nHL_ : number;\nIX : number;\nIY : number;\nSP : number;\nPC : number;\nIR : number;\niff1 : number;\niff2 : number;\nim : number;\nhalted : boolean;\ndo_delayed_di : boolean;\ndo_delayed_ei : boolean;\ncycle_counter : number;\n}\n\nexport class Z80 implements CPU, InstructionBased, IOBusConnected, SavesState<Z80State>, Interruptable<number> {\n\n cpu;\n interruptType;\n memBus : Bus;\n ioBus : Bus;\n retryInterrupts : boolean = false;\n retryData : number = -1;\n \n private buildCPU() {\n if (this.memBus && this.ioBus) {\n this.cpu = new FastZ80({\n mem_read: this.memBus.read.bind(this.memBus),\n mem_write: this.memBus.write.bind(this.memBus),\n io_read: this.ioBus.read.bind(this.ioBus),\n io_write: this.ioBus.write.bind(this.ioBus),\n });\n }\n }\n connectMemoryBus(bus:Bus) {\n this.memBus = bus;\n this.buildCPU();\n }\n connectIOBus(bus:Bus) {\n this.ioBus = bus;\n this.buildCPU();\n }\n advanceInsn() {\n if (this.retryInterrupts && this.retryData >= 0 && this.cpu.interrupt(false, this.retryData)) {\n this.retryData = -1;\n }\n return this.cpu.advanceInsn();\n }\n reset() {\n this.cpu.reset();\n }\n interrupt(data:number) {\n if (!this.cpu.interrupt(false, data) && this.retryInterrupts) {\n this.retryData = data;\n }\n }\n NMI() {\n this.cpu.interrupt(true, 0);\n }\n getSP() {\n return this.cpu.getSP();\n }\n getPC() {\n return this.cpu.getPC();\n }\n isHalted() {\n return this.cpu.getHalted();\n }\n saveState() {\n return this.cpu.saveState();\n }\n loadState(s) {\n this.cpu.loadState(s);\n }\n isStable() { return true; }\n // TODO: metadata\n // TODO: disassembler\n}\n", "\nimport { SampledAudioSink } from \"./devices\";\n\n// from TSS\ndeclare var MasterChannel, AudioLooper, PsgDeviceChannel;\n\nexport class MasterAudio {\n master = new MasterChannel();\n looper;\n start() {\n if (!this.looper) {\n this.looper = new AudioLooper(512);\n this.looper.setChannel(this.master);\n this.looper.activate();\n }\n }\n stop() {\n if (this.looper) {\n this.looper.setChannel(null);\n this.looper = null;\n }\n }\n}\n\nexport class AY38910_Audio {\n master : MasterAudio;\n psg = new PsgDeviceChannel();\n curreg = 0;\n\n constructor(master : MasterAudio) {\n this.master = master;\n this.psg.setMode(PsgDeviceChannel.MODE_SIGNED);\n this.psg.setDevice(PsgDeviceChannel.DEVICE_AY_3_8910);\n master.master.addChannel(this.psg);\n }\n\n reset() {\n for (var i=15; i>=0; i--) {\n this.selectRegister(i);\n this.setData(0);\n }\n }\n selectRegister(val : number) {\n this.curreg = val & 0xf;\n }\n setData(val : number) {\n this.psg.writeRegisterAY(this.curreg, val & 0xff);\n }\n readData() {\n return this.psg.readRegister(this.curreg);\n }\n currentRegister() { return this.curreg; }\n}\n\nexport class SN76489_Audio {\n master : MasterAudio;\n psg = new PsgDeviceChannel();\n\n constructor(master : MasterAudio) {\n this.master = master;\n this.psg.setMode(PsgDeviceChannel.MODE_SIGNED);\n this.psg.setDevice(PsgDeviceChannel.DEVICE_SN76489);\n master.master.addChannel(this.psg);\n }\n reset() {\n // TODO\n }\n setData(val : number) {\n this.psg.writeRegisterSN(0, val & 0xff);\n }\n}\n\n// https://en.wikipedia.org/wiki/POKEY\n// https://user.xmission.com/~trevin/atari/pokey_regs.html\n// http://krap.pl/mirrorz/atari/homepage.ntlworld.com/kryten_droid/Atari/800XL/atari_hw/pokey.htm\n\nexport function newPOKEYAudio(count:number) {\n var audio = new MasterAudio();\n for (var i=1; i<=count; i++) {\n var pokey = new POKEYDeviceChannel();\n audio['pokey'+i] = pokey; // TODO: cheezy\n audio.master.addChannel(pokey);\n }\n return audio;\n}\n\nfunction combinePolys(a, b) {\n var arr = new Uint8Array(a.length * b.length);\n var n = 0;\n for (var i=0; i<arr.length; i++) {\n arr[i] = b[n % b.length];\n if (a[i % a.length]) n++;\n }\n return arr;\n}\n\nfunction divideBy(n) {\n var arr = new Uint8Array(n*2);\n arr.fill(1, 0, n);\n return arr;\n}\n\nexport var POKEYDeviceChannel = function() {\n\n /* definitions for AUDCx (D201, D203, D205, D207) */\n var NOTPOLY5 = 0x80 /* selects POLY5 or direct CLOCK */\n var POLY4 = 0x40 /* selects POLY4 or POLY17 */\n var PURE = 0x20 /* selects POLY4/17 or PURE tone */\n var VOL_ONLY = 0x10 /* selects VOLUME OUTPUT ONLY */\n var VOLUME_MASK = 0x0f /* volume mask */\n\n /* definitions for AUDCTL (D208) */\n var POLY9 = 0x80 /* selects POLY9 or POLY17 */\n var CH1_179 = 0x40 /* selects 1.78979 MHz for Ch 1 */\n var CH3_179 = 0x20 /* selects 1.78979 MHz for Ch 3 */\n var CH1_CH2 = 0x10 /* clocks channel 1 w/channel 2 */\n var CH3_CH4 = 0x08 /* clocks channel 3 w/channel 4 */\n var CH1_FILTER = 0x04 /* selects channel 1 high pass filter */\n var CH2_FILTER = 0x02 /* selects channel 2 high pass filter */\n var CLOCK_15 = 0x01 /* selects 15.6999kHz or 63.9210kHz */\n\n /* for accuracy, the 64kHz and 15kHz clocks are exact divisions of\n the 1.79MHz clock */\n var DIV_64 = 28 /* divisor for 1.79MHz clock to 64 kHz */\n var DIV_15 = 114 /* divisor for 1.79MHz clock to 15 kHz */\n\n /* the size (in entries) of the 4 polynomial tables */\n var POLY4_SIZE = 0x000f\n var POLY5_SIZE = 0x001f\n var POLY9_SIZE = 0x01ff\n\n var POLY17_SIZE = 0x0001ffff /* else use the full 17 bits */\n\n /* channel/chip definitions */\n var CHAN1 = 0\n var CHAN2 = 1\n var CHAN3 = 2\n var CHAN4 = 3\n var CHIP1 = 0\n var CHIP2 = 4\n var CHIP3 = 8\n var CHIP4 = 12\n var SAMPLE = 127\n\n var FREQ_17_EXACT = 1789790.0 /* exact 1.79 MHz clock freq */\n var FREQ_17_APPROX = 1787520.0 /* approximate 1.79 MHz clock freq */\n\n // LFSR sequences\n var bit1 = new Uint8Array( [ 1 ] );\n var bit2 = new Uint8Array( [ 0,1 ] ); // TODO?\n var bit4 = new Uint8Array( [ 1,1,0,1,1,1,0,0,0,0,1,0,1,0,0 ] );\n var bit5 = new Uint8Array( [ 0,0,1,1,0,0,0,1,1,1,1,0,0,1,0,1,0,1,1,0,1,1,1,0,1,0,0,0,0,0,1 ] );\n var bit9 = new Uint8Array( [ 0,0,1,0,1,0,0,0,1,0,0,0,0,0,0,0,1,0,1,1,1,0,0,1,0,1,0,0,1,1,1,1,1,0,0,1,1,0,1,1,0,1,0,1,1,1,0,1,1,0,0,1,0,0,1,1,1,1,0,1,0,0,0,0,1,1,0,1,1,0,0,0,1,0,0,0,1,1,1,1,0,1,0,1,1,0,1,0,1,0,0,0,0,1,1,0,1,0,1,0,0,0,1,0,1,0,0,0,1,1,1,0,0,1,1,0,1,1,0,0,1,1,1,1,1,0,0,1,1,0,0,0,1,1,0,1,0,0,0,1,1,0,0,1,1,1,1,0,0,1,0,0,0,1,1,1,0,0,1,1,0,1,0,1,1,0,1,1,0,1,0,0,1,0,0,1,1,1,1,1,1,0,1,1,1,1,0,1,1,0,0,0,0,1,1,1,1,1,0,0,0,1,0,0,0,0,1,0,0,0,1,0,1,0,1,1,0,0,0,0,1,0,1,1,1,1,0,1,0,0,0,1,1,0,0,0,1,1,1,0,1,1,1,0,1,0,0,0,0,0,0,0,0,1,0,1,0,0,1,0,0,0,0,1,1,1,0,0,0,1,1,1,0,0,1,1,0,0,1,0,0,1,0,1,1,0,0,0,0,1,0,0,0,1,0,0,0,1,0,1,1,1,1,0,0,0,1,1,1,0,0,0,1,0,0,1,1,1,1,0,1,1,1,1,1,1,1,0,1,1,1,1,1,1,0,1,1,0,1,0,1,1,1,1,0,0,1,0,1,0,1,1,1,0,0,0,0,0,1,1,0,1,1,0,0,0,1,0,1,0,1,0,0,0,0,1,0,1,1,1,0,0,0,0,1,0,0,1,0,1,0,0,0,1,0,1,1,1,0,0,1,1,1,1,1,1,1,0,0,0,0,0,1,0,0,1,1,0,1,0,0,1,0,0,0,1,0,0,1,0,1,0,0,0,1,1,0,1,0,0,0,0,0,1,1,1,1,0,0,1,0,0,1,0,1,1,1,1,1,1,1,0,1,0,0,1,0,0,0,1,1,0,1,1,1,0,0,0,1,0,1,0,0,1,0,1,0,1,0,1,1,1,0,0,1,0,1,1,0,0,1,1,1,1,1,0,0,0,1,1,0 ] );\n var bit15 = new Uint8Array( [1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0] );\n var bit31 = new Uint8Array( [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0] );\n var bit17 = new Uint8Array(1<<14);\n for (var i=0; i<bit17.length; i++) {\n bit17[i] = Math.random() > 0.5 ? 1 : 0;\n }\n var bit17_5 = combinePolys(bit17, bit5);\n var bit5_4 = combinePolys(bit5, bit4);\n var wavetones = [\n bit17_5, bit5, bit5_4, bit5,\n bit17, bit2, bit4, bit2\n ];\n // TIA\n var div2 = divideBy(2);\n var div6 = divideBy(6);\n var div31 = divideBy(31);\n var div93 = divideBy(93);\n var bit15_4 = combinePolys(bit15, bit4);\n var bit5_2 = combinePolys(bit5, div2);\n var bit5_6 = combinePolys(bit5, div6);\n var tiawavetones = [\n bit1, bit4, bit15_4, bit5_4,\n div2, div2, div31, bit5_2,\n bit9, bit5, div31, bit1,\n div6, div6, div93, bit5_6\n ];\n \n // registers\n var regs = new Uint8Array(16);\n var counters = new Float32Array(4);\n var deltas = new Float32Array(4);\n var volume = new Float32Array(4);\n var audc = new Uint8Array(4);\n var waveforms = [bit1, bit1, bit1, bit1];\n var buffer;\n var sampleRate;\n var clock, baseDelta;\n var dirty = true;\n\n //\n\n this.setBufferLength = function (length) {\n buffer = new Int32Array(length);\n };\n\n this.getBuffer = function () {\n return buffer;\n };\n\n this.setSampleRate = function (rate) {\n sampleRate = rate;\n baseDelta = FREQ_17_EXACT / rate;\n };\n\n function updateValues(addr) {\n var ctrl = regs[8];\n var base = (ctrl & CLOCK_15) ? DIV_15 : DIV_64;\n var div;\n var i = addr & 4;\n var j = i>>1;\n var k = i>>2;\n if (ctrl & (CH1_CH2>>k)) {\n if (ctrl & (CH1_179>>k))\n div = regs[i+2] * 256 + regs[i+0] + 7;\n else\n div = (regs[i+2] * 256 + regs[i+0] + 1) * base;\n deltas[j+1] = baseDelta / div;\n deltas[j+0] = 0;\n } else {\n if (ctrl & (CH1_179>>k)) {\n div = regs[i+0] + 4;\n } else {\n div = (regs[i+0] + 1) * base;\n }\n deltas[j+0] = baseDelta / div;\n div = (regs[i+2] + 1) * base;\n deltas[j+1] = baseDelta / div;\n }\n //console.log(addr, ctrl.toString(16), div, deltas[j+0], deltas[j+1]);\n }\n\n this.setRegister = function(addr, value) {\n addr &= 0xf;\n value &= 0xff;\n if (regs[addr] != value) {\n regs[addr] = value;\n switch (addr) {\n case 0:\n case 2:\n case 4:\n case 6: // AUDF\n case 8: // ctrl\n dirty = true;\n break;\n case 1:\n case 3:\n case 5:\n case 7: // AUDC\n volume[addr>>1] = value & 0xf;\n waveforms[addr>>1] = wavetones[value>>5];\n break;\n }\n }\n }\n\n this.getRegister = function(addr) {\n addr &= 0xf;\n return regs[addr];\n }\n \n this.setTIARegister = function(addr, value) {\n switch (addr) {\n case 0x17:\n case 0x18:\n regs[(addr&1)*4] = value & 0x1f;\n dirty = true;\n break;\n case 0x15:\n case 0x16:\n waveforms[(addr&1)*2] = tiawavetones[value & 0xf];\n break;\n case 0x19:\n case 0x1a:\n volume[(addr&1)*2] = value & 0xf;\n break;\n }\n }\n\n this.generate = function (length) {\n if (dirty) {\n updateValues(0);\n updateValues(4);\n dirty = false;\n }\n for (var s=0; s<length; s+=2) {\n var sample = 0;\n for (var i=0; i<4; i++) {\n var d = deltas[i];\n var v = volume[i];\n if (d > 0 && d < 1 && v > 0) {\n var wav = waveforms[i];\n var cnt = counters[i] += d;\n if (cnt > wav.length) {\n cnt = counters[i] = cnt - Math.floor(cnt / wav.length) * wav.length;\n }\n var on = wav[Math.floor(cnt)];\n if (on) {\n sample += v;\n }\n }\n }\n sample *= 64;\n buffer[s] = sample;\n buffer[s+1] = sample;\n }\n }\n}\n\n////// Worker sound\n\nexport var WorkerSoundChannel = function(worker) {\n var sampleRate;\n var output;\n var pending = [];\n var pendingLength = 0;\n\n worker.onmessage = function(e) {\n if (e && e.data && e.data.samples && output) {\n pending.push(e.data.samples);\n pendingLength += e.data.samples.length;\n }\n };\n\n this.setBufferLength = function (length) {\n output = new Int16Array(length);\n //worker.postMessage({bufferLength:length,numChannels:2});\n pendingLength = 0;\n };\n\n this.getBuffer = function () {\n return output;\n };\n\n this.setSampleRate = function (rate) {\n sampleRate = rate;\n worker.postMessage({sampleRate:rate});\n };\n\n this.generate = function (length) {\n if (pendingLength < length*3) {\n //console.log(length, pendingLength);\n output.fill(0);\n return; // TODO: send sync msg?\n }\n for (var i=0; i<output.length;) {\n if (pending.length == 0) break; // TODO?\n var buf = pending.shift();\n pendingLength -= buf.length;\n var l = output.length-i;\n if (buf.length < l) {\n output.set(buf, i);\n } else {\n output.set(buf.slice(0, l), i);\n pending.unshift(buf.slice(l));\n pendingLength += buf.length-l;\n }\n i += buf.length;\n }\n }\n\n}\n\n// SampleAudio\n\nexport var SampleAudio = function(clockfreq) {\n var self = this;\n var sfrac, sinc, accum;\n var buffer, bufpos, bufferlist;\n var idrain, ifill;\n var nbuffers = 4;\n\n function mix(ape) {\n var buflen=ape.outputBuffer.length;\n var lbuf = ape.outputBuffer.getChannelData(0);\n var m = this.module;\n if (!m) m = ape.srcElement.module;\n if (!m) return;\n if (m.callback) {\n m.callback(lbuf);\n return;\n } else {\n var buf = bufferlist[idrain];\n for (var i=0; i<lbuf.length; i++) {\n lbuf[i] = buf[i];\n //lbuf[i] = (i&128) ? 1.0 : 0.33;\n }\n idrain = (idrain + 1) % bufferlist.length;\n }\n }\n \n function clearBuffers() {\n if (bufferlist)\n for (var buf of bufferlist)\n buf.fill(0);\n }\n\n function createContext() {\n var AudioContext = window['AudioContext'] || window['webkitAudioContext'] || window['mozAudioContext'];\n if (! AudioContext) {\n console.log(\"no web audio context\");\n return;\n }\n var ctx : AudioContext = new AudioContext();\n self.context = ctx;\n self.sr=self.context.sampleRate;\n self.bufferlen=2048;\n\n // remove DC bias\n self.filterNode=self.context.createBiquadFilter();\n self.filterNode.type='lowshelf';\n self.filterNode.frequency.value=100;\n self.filterNode.gain.value=-6;\n\n // mixer\n if ( typeof self.context.createScriptProcessor === 'function') {\n self.mixerNode=self.context.createScriptProcessor(self.bufferlen, 1, 1);\n } else {\n self.mixerNode=self.context.createJavaScriptNode(self.bufferlen, 1, 1);\n }\n\n self.mixerNode.module=self;\n self.mixerNode.onaudioprocess=mix;\n\n // compressor for a bit of volume boost, helps with multich tunes\n self.compressorNode=self.context.createDynamicsCompressor();\n\n // patch up some cables :)\n self.mixerNode.connect(self.filterNode);\n self.filterNode.connect(self.compressorNode);\n self.compressorNode.connect(self.context.destination);\n }\n\n this.start = function() {\n if (this.context) {\n // Chrome autoplay (https://goo.gl/7K7WLu)\n if (this.context.state == 'suspended') {\n this.context.resume();\n }\n return; // already created\n }\n createContext();\t\t// create it\n if (!this.context) return; // not created?\n sinc = this.sr * 1.0 / clockfreq;\n sfrac = 0;\n accum = 0;\n bufpos = 0;\n bufferlist = [];\n idrain = 1;\n ifill = 0;\n for (var i=0; i<nbuffers; i++) {\n var arrbuf = new ArrayBuffer(self.bufferlen*4);\n bufferlist[i] = new Float32Array(arrbuf);\n }\n buffer = bufferlist[0];\n }\n \n this.stop = function() {\n this.context && this.context.suspend && this.context.suspend();\n clearBuffers(); // just in case it doesn't stop immediately\n }\n\n this.close = function() {\n if (this.context) {\n this.context.close();\n this.context = null;\n }\n }\n\n this.addSingleSample = function(value) {\n if (!buffer) return;\n buffer[bufpos++] = value;\n if (bufpos >= buffer.length) {\n bufpos = 0;\n bufferlist[ifill] = buffer;\n var inext = (ifill + 1) % bufferlist.length;\n if (inext == idrain) {\n ifill = Math.floor(idrain + nbuffers/2) % bufferlist.length;\n //console.log('SampleAudio: skipped buffer', idrain, ifill); // TODO\n } else {\n ifill = inext;\n }\n buffer = bufferlist[ifill];\n }\n }\n\n this.feedSample = function(value, count) {\n accum += value * count;\n sfrac += sinc * count;\n if (sfrac >= 1) {\n accum /= sfrac;\n while (sfrac >= 1) {\n this.addSingleSample(accum * sinc);\n sfrac -= 1;\n }\n accum *= sfrac;\n }\n }\n \n}\n\n\nexport class SampledAudio {\n sa;\n constructor(sampleRate : number) {\n this.sa = new SampleAudio(sampleRate);\n }\n feedSample(value:number, count:number) {\n this.sa.feedSample(value, count);\n }\n start() {\n this.sa.start();\n }\n stop() {\n this.sa.stop();\n }\n}\n\ninterface TssChannel {\n setBufferLength(len : number) : void;\n setSampleRate(rate : number) : void;\n getBuffer() : number[];\n generate(numSamples : number) : void;\n}\n\nexport class TssChannelAdapter {\n channels : TssChannel[];\n audioGain = 1.0 / 8192;\n bufferLength : number;\n\n constructor(chans, oversample:number, sampleRate:number) {\n this.bufferLength = oversample * 2;\n this.channels = chans.generate ? [chans] : chans; // array or single channel\n this.channels.forEach((c) => {\n c.setBufferLength(this.bufferLength);\n c.setSampleRate(sampleRate);\n });\n }\n\n generate(sink:SampledAudioSink) {\n var l = this.bufferLength;\n var bufs = this.channels.map((ch) => ch.getBuffer());\n this.channels.forEach((ch) => {\n ch.generate(l);\n });\n for (let i=0; i<l; i+=2) {\n var total = 0;\n bufs.forEach((buf) => total += buf[i]);\n sink.feedSample(total * this.audioGain, 1);\n };\n }\n}\n\n", "\nimport { Probeable, ProbeAll } from \"./devices\";\n\nexport enum ProbeFlags {\n CLOCKS\t = 0x00000000,\n EXECUTE\t = 0x01000000,\n INTERRUPT\t= 0x08000000,\n ILLEGAL\t = 0x09000000,\n SP_PUSH\t = 0x0a000000,\n SP_POP\t = 0x0b000000,\n HAS_VALUE = 0x10000000,\n MEM_READ\t= 0x12000000,\n MEM_WRITE\t= 0x13000000,\n IO_READ\t = 0x14000000,\n IO_WRITE\t= 0x15000000,\n VRAM_READ\t= 0x16000000,\n VRAM_WRITE= 0x17000000,\n DMA_READ = 0x18000000,\n DMA_WRITE = 0x19000000,\n WAIT = 0x1f000000,\n SCANLINE\t= 0x7e000000,\n FRAME\t\t = 0x7f000000,\n}\n\nclass ProbeFrame {\n data : Uint32Array;\n len : number;\n}\n\nexport class ProbeRecorder implements ProbeAll {\n\n m : Probeable; // machine to probe\n buf : Uint32Array; // buffer\n idx : number = 0; // index into buffer\n sl : number = 0; // scanline\n cur_sp = -1; // last stack pointer\n singleFrame : boolean = true; // clear between frames\n\n constructor(m:Probeable, buflen?:number) {\n this.m = m;\n this.reset(buflen || 0x100000);\n }\n start() {\n this.m.connectProbe(this);\n }\n stop() {\n this.m.connectProbe(null);\n }\n reset(newbuflen? : number) {\n if (newbuflen) this.buf = new Uint32Array(newbuflen);\n this.sl = 0;\n this.cur_sp = -1;\n this.clear();\n }\n clear() {\n this.idx = 0;\n }\n logData(a:number) {\n this.log(a);\n }\n log(a:number) {\n // TODO: coalesce READ and EXECUTE and PUSH/POP\n if (this.idx >= this.buf.length) return;\n this.buf[this.idx++] = a;\n }\n relog(a:number) {\n this.buf[this.idx-1] = a;\n }\n lastOp() {\n if (this.idx > 0)\n return this.buf[this.idx-1] & 0xff000000;\n else\n return -1;\n }\n lastAddr() {\n if (this.idx > 0)\n return this.buf[this.idx-1] & 0xffffff;\n else\n return -1;\n }\n addLogBuffer(src: Uint32Array) {\n if (this.idx + src.length > this.buf.length) {\n src = src.slice(0, this.buf.length - this.idx);\n }\n this.buf.set(src, this.idx);\n this.idx += src.length;\n}\n logClocks(clocks:number) {\n clocks |= 0;\n if (clocks > 0) {\n if (this.lastOp() == ProbeFlags.CLOCKS)\n this.relog((this.lastAddr() + clocks) | ProbeFlags.CLOCKS); // coalesce clocks\n else\n this.log(clocks | ProbeFlags.CLOCKS);\n }\n }\n logNewScanline() {\n this.log(ProbeFlags.SCANLINE);\n this.sl++;\n }\n logNewFrame() {\n this.log(ProbeFlags.FRAME);\n this.sl = 0;\n if (this.singleFrame) this.clear();\n }\n logExecute(address:number, SP:number) {\n // record stack pushes/pops (from last instruction)\n if (this.cur_sp !== SP) {\n if (SP < this.cur_sp) {\n this.log(ProbeFlags.SP_PUSH | SP);\n }\n if (SP > this.cur_sp) {\n this.log(ProbeFlags.SP_POP | SP);\n }\n this.cur_sp = SP;\n }\n this.log(address | ProbeFlags.EXECUTE);\n }\n logInterrupt(type:number) {\n this.log(type | ProbeFlags.INTERRUPT);\n }\n logValue(address:number, value:number, op:number) {\n this.log((address & 0xffff) | ((value & 0xff)<<16) | op);\n }\n logRead(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.MEM_READ);\n }\n logWrite(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.MEM_WRITE);\n }\n logIORead(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.IO_READ);\n }\n logIOWrite(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.IO_WRITE);\n }\n logVRAMRead(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.VRAM_READ);\n }\n logVRAMWrite(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.VRAM_WRITE);\n }\n logIllegal(address:number) {\n this.log(address | ProbeFlags.ILLEGAL);\n }\n logWait(address:number) {\n this.log(address | ProbeFlags.WAIT);\n }\n logDMARead(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.DMA_READ);\n }\n logDMAWrite(address:number, value:number) {\n this.logValue(address, value, ProbeFlags.DMA_WRITE);\n }\n countEvents(op : number) : number {\n var count = 0;\n for (var i=0; i<this.idx; i++) {\n if ((this.buf[i] & 0xff000000) == op)\n count++;\n }\n return count;\n }\n countClocks() : number {\n var count = 0;\n for (var i=0; i<this.idx; i++) {\n if ((this.buf[i] & 0xff000000) == ProbeFlags.CLOCKS)\n count += this.buf[i] & 0xffff;\n }\n return count;\n }\n\n}\n", "\nexport interface SavesState<S> {\n saveState() : S;\n loadState(state:S) : void;\n}\n\nexport interface Bus {\n read(a:number) : number;\n write(a:number, v:number) : void;\n readConst?(a:number) : number;\n}\n\nexport interface ClockBased {\n advanceClock() : void;\n}\n\nexport interface InstructionBased {\n advanceInsn() : number;\n}\n\nexport type TrapCondition = () => boolean;\n\nexport interface FrameBased {\n advanceFrame(trap:TrapCondition) : number;\n}\n\nexport interface VideoSource {\n getVideoParams() : VideoParams;\n connectVideo(pixels:Uint32Array) : void;\n}\n\nexport interface RasterFrameBased extends FrameBased, VideoSource {\n getRasterY() : number;\n getRasterX() : number;\n}\n\nexport interface VideoParams {\n width : number;\n height : number;\n overscan? : boolean;\n rotate? : number;\n videoFrequency? : number; // default = 60\n aspect? : number;\n}\n\n// TODO: frame buffer optimization (apple2, etc)\n\nexport interface SampledAudioParams {\n sampleRate : number;\n stereo : boolean;\n}\n\nexport interface SampledAudioSink {\n feedSample(value:number, count:number) : void;\n //sendAudioFrame(samples:Uint16Array) : void;\n}\n\nexport interface SampledAudioSource {\n getAudioParams() : SampledAudioParams;\n connectAudio(audio : SampledAudioSink) : void;\n}\n\nexport interface AcceptsROM {\n loadROM(data:Uint8Array, title?:string) : void;\n}\n\nexport interface AcceptsBIOS {\n loadBIOS(data:Uint8Array, title?:string) : void;\n}\n\nexport interface Resettable {\n reset() : void;\n}\n\nexport interface MemoryBusConnected {\n connectMemoryBus(bus:Bus) : void;\n}\n\nexport interface IOBusConnected {\n connectIOBus(bus:Bus) : void;\n}\n\nexport interface CPU extends MemoryBusConnected, Resettable, SavesState<any> {\n getPC() : number;\n getSP() : number;\n isStable() : boolean;\n}\n\nexport interface HasCPU extends Resettable {\n cpu : CPU;\n}\n\nexport interface Interruptable<IT> {\n interrupt(type:IT) : void;\n}\n\nexport interface SavesInputState<CS> {\n loadControlsState(cs:CS) : void;\n saveControlsState() : CS;\n}\n\nexport interface AcceptsKeyInput {\n setKeyInput(key:number, code:number, flags:number) : void;\n}\n\nexport interface AcceptsPaddleInput {\n setPaddleInput(controller:number, value:number) : void;\n}\n\n// TODO: interface not yet used (setKeyInput() handles joystick)\nexport interface AcceptsJoyInput {\n setJoyInput(joy:number, bitmask:number) : void;\n}\n\n// SERIAL I/O\n\nexport interface SerialEvent {\n op: 'read' | 'write';\n value: number;\n nbits: number;\n}\n\n// TODO: all these needed?\nexport interface SerialIOInterface {\n // from machine to platform\n clearToSend() : boolean;\n sendByte(b : number);\n // from platform to machine\n byteAvailable() : boolean;\n recvByte() : number;\n // implement these too\n reset() : void;\n advance(clocks: number) : void;\n// refresh() : void;\n}\n\nexport interface HasSerialIO {\n connectSerialIO(serial: SerialIOInterface);\n serialOut?: SerialEvent[]; // outgoing event log\n serialIn?: SerialEvent[]; // incoming queue\n}\n\n/// PROFILER\n\nexport interface Probeable {\n connectProbe(probe: ProbeAll) : void;\n}\n\nexport interface ProbeTime {\n logClocks(clocks:number);\n logNewScanline();\n logNewFrame();\n}\n\nexport interface ProbeCPU {\n logExecute(address:number, SP:number);\n logInterrupt(type:number);\n logIllegal(address:number);\n logWait(address:number);\n}\n\nexport interface ProbeBus {\n logRead(address:number, value:number);\n logWrite(address:number, value:number);\n logDMARead(address:number, value:number);\n logDMAWrite(address:number, value:number);\n}\n\nexport interface ProbeIO {\n logIORead(address:number, value:number);\n logIOWrite(address:number, value:number);\n}\n\nexport interface ProbeVRAM {\n logVRAMRead(address:number, value:number);\n logVRAMWrite(address:number, value:number);\n}\n\nexport interface ProbeAll extends ProbeTime, ProbeCPU, ProbeBus, ProbeIO, ProbeVRAM {\n logData(data:number); // entire 32 bits\n addLogBuffer(src: Uint32Array);\n}\n\nexport class NullProbe implements ProbeAll {\n logClocks()\t\t{}\n logNewScanline()\t{}\n logNewFrame()\t\t{}\n logExecute()\t\t{}\n logInterrupt()\t{}\n logRead()\t\t{}\n logWrite()\t\t{}\n logIORead()\t\t{}\n logIOWrite()\t\t{}\n logVRAMRead()\t\t{}\n logVRAMWrite()\t{}\n logIllegal()\t\t{}\n logWait()\t\t{}\n logDMARead()\t\t{}\n logDMAWrite()\t\t{}\n logData() {}\n addLogBuffer(src: Uint32Array) {}\n}\n\n/// CONVENIENCE\n\nexport interface BasicMachineControlsState {\n inputs: Uint8Array;\n}\n\nexport interface BasicMachineState extends BasicMachineControlsState {\n c: any; // TODO\n ram: Uint8Array;\n}\n\nexport abstract class BasicHeadlessMachine implements HasCPU, Bus, AcceptsROM, Probeable,\n SavesState<BasicMachineState>, SavesInputState<BasicMachineControlsState> {\n\n abstract cpuFrequency : number;\n abstract defaultROMSize : number;\n\n abstract cpu : CPU;\n abstract ram : Uint8Array; \n\n rom : Uint8Array;\n inputs : Uint8Array = new Uint8Array(32);\n handler : (key,code,flags) => void; // keyboard handler\n\n nullProbe = new NullProbe();\n probe : ProbeAll = this.nullProbe;\n \n abstract read(a:number) : number;\n abstract write(a:number, v:number) : void;\n\n setKeyInput(key:number, code:number, flags:number) : void {\n this.handler && this.handler(key,code,flags);\n }\n connectProbe(probe: ProbeAll) : void {\n this.probe = probe || this.nullProbe;\n }\n reset() {\n this.cpu.reset();\n }\n loadROM(data:Uint8Array, title?:string) : void {\n if (!this.rom) this.rom = new Uint8Array(this.defaultROMSize);\n this.rom.set(data);\n }\n loadState(state) {\n this.cpu.loadState(state.c);\n this.ram.set(state.ram);\n this.inputs.set(state.inputs);\n }\n saveState() {\n return {\n c:this.cpu.saveState(),\n ram:this.ram.slice(0),\n inputs:this.inputs.slice(0),\n };\n }\n loadControlsState(state) {\n this.inputs.set(state.inputs);\n }\n saveControlsState() {\n return {\n inputs:this.inputs.slice(0)\n };\n }\n advanceCPU() {\n var c = this.cpu as any;\n var n = 1;\n if (this.cpu.isStable()) { this.probe.logExecute(this.cpu.getPC(), this.cpu.getSP()); }\n if (c.advanceClock) { c.advanceClock(); }\n else if (c.advanceInsn) { n = c.advanceInsn(1); }\n this.probe.logClocks(n);\n return n;\n }\n probeMemoryBus(membus:Bus) : Bus {\n return {\n read: (a) => {\n let val = membus.read(a);\n this.probe.logRead(a,val);\n return val;\n },\n write: (a,v) => {\n this.probe.logWrite(a,v);\n membus.write(a,v);\n }\n };\n }\n connectCPUMemoryBus(membus:Bus) : void {\n this.cpu.connectMemoryBus(this.probeMemoryBus(membus));\n }\n probeIOBus(iobus:Bus) : Bus {\n return {\n read: (a) => {\n let val = iobus.read(a);\n this.probe.logIORead(a,val);\n return val;\n },\n write: (a,v) => {\n this.probe.logIOWrite(a,v);\n iobus.write(a,v);\n }\n };\n }\n probeDMABus(iobus:Bus) : Bus {\n return {\n read: (a) => {\n let val = iobus.read(a);\n this.probe.logDMARead(a,val);\n return val;\n },\n write: (a,v) => {\n this.probe.logDMAWrite(a,v);\n iobus.write(a,v);\n }\n };\n }\n connectCPUIOBus(iobus:Bus) : void {\n this.cpu['connectIOBus'](this.probeIOBus(iobus));\n }\n}\n\nexport abstract class BasicMachine extends BasicHeadlessMachine implements SampledAudioSource {\n\n abstract canvasWidth : number;\n abstract numVisibleScanlines : number;\n abstract sampleRate : number;\n overscan : boolean = false;\n rotate : number = 0;\n aspectRatio : number;\n \n pixels : Uint32Array;\n audio : SampledAudioSink;\n\n scanline : number;\n \n getAudioParams() : SampledAudioParams {\n return {sampleRate:this.sampleRate, stereo:false};\n }\n connectAudio(audio : SampledAudioSink) : void {\n this.audio = audio;\n }\n getVideoParams() : VideoParams {\n return {width:this.canvasWidth,\n height:this.numVisibleScanlines,\n aspect:this.aspectRatio,\n overscan:this.overscan,\n rotate:this.rotate};\n }\n connectVideo(pixels:Uint32Array) : void {\n this.pixels = pixels;\n }\n}\n\nexport abstract class BasicScanlineMachine extends BasicMachine implements RasterFrameBased {\n\n abstract numTotalScanlines : number;\n abstract cpuCyclesPerLine : number;\n\n abstract startScanline() : void;\n abstract drawScanline() : void;\n\n frameCycles : number;\n \n advanceFrame(trap: TrapCondition) : number {\n this.preFrame();\n var endLineClock = 0;\n var steps = 0;\n this.probe.logNewFrame();\n this.frameCycles = 0;\n for (var sl=0; sl<this.numTotalScanlines; sl++) {\n endLineClock += this.cpuCyclesPerLine; // could be fractional\n this.scanline = sl;\n this.startScanline();\n while (this.frameCycles < endLineClock) {\n if (trap && trap()) {\n sl = 999;\n break;\n }\n this.frameCycles += this.advanceCPU();\n steps++;\n }\n this.drawScanline();\n this.probe.logNewScanline();\n this.probe.logClocks(Math.floor(this.frameCycles - endLineClock)); // remainder of prev. line\n }\n this.postFrame();\n return steps; // TODO: return steps, not clock? for recorder\n }\n preFrame() { }\n postFrame() { }\n getRasterY() { return this.scanline; }\n getRasterX() { return this.frameCycles % this.cpuCyclesPerLine; }\n}\n", "\nimport { hex } from \"../util\";\n\nconst Z80_OPS = [\"nop\",\"ld bc,xx\",\"ld (bc),a\",\"inc bc\",\"inc b\",\"dec b\",\"ld b,x\",\"rlca\",\"ex af,af'\",\"add hl,bc\",\"ld a,(bc)\",\"dec bc\",\"inc c\",\"dec c\",\"ld c,x\",\"rrca\",\"djnz x\",\"ld de,xx\",\"ld (de),a\",\"inc de\",\"inc d\",\"dec d\",\"ld d,x\",\"rla\",\"jr x\",\"add hl,de\",\"ld a,(de)\",\"dec de\",\"inc e\",\"dec e\",\"ld e,x\",\"rra\",\"jr nz,x\",\"ld hl,xx\",\"ld (xx),hl\",\"inc hl\",\"inc h\",\"dec h\",\"ld h,x\",\"daa\",\"jr z,x\",\"add hl,hl\",\"ld hl,(xx)\",\"dec hl\",\"inc l\",\"dec l\",\"ld l,x\",\"cpl\",\"jr nc,x\",\"ld sp,xx\",\"ld (xx),a\",\"inc sp\",\"inc (hl)\",\"dec (hl)\",\"ld (hl),x\",\"scf\",\"jr c,x\",\"add hl,sp\",\"ld a,(xx)\",\"dec sp\",\"inc a\",\"dec a\",\"ld a,x\",\"ccf\",\"ld b,b\",\"ld b,c\",\"ld b,d\",\"ld b,e\",\"ld b,h\",\"ld b,l\",\"ld b,(hl)\",\"ld b,a\",\"ld c,b\",\"ld c,c\",\"ld c,d\",\"ld c,e\",\"ld c,h\",\"ld c,l\",\"ld c,(hl)\",\"ld c,a\",\"ld d,b\",\"ld d,c\",\"ld d,d\",\"ld d,e\",\"ld d,h\",\"ld d,l\",\"ld d,(hl)\",\"ld d,a\",\"ld e,b\",\"ld e,c\",\"ld e,d\",\"ld e,e\",\"ld e,h\",\"ld e,l\",\"ld e,(hl)\",\"ld e,a\",\"ld h,b\",\"ld h,c\",\"ld h,d\",\"ld h,e\",\"ld h,h\",\"ld h,l\",\"ld h,(hl)\",\"ld h,a\",\"ld l,b\",\"ld l,c\",\"ld l,d\",\"ld l,e\",\"ld l,h\",\"ld l,l\",\"ld l,(hl)\",\"ld l,a\",\"ld (hl),b\",\"ld (hl),c\",\"ld (hl),d\",\"ld (hl),e\",\"ld (hl),h\",\"ld (hl),l\",\"halt\",\"ld (hl),a\",\"ld a,b\",\"ld a,c\",\"ld a,d\",\"ld a,e\",\"ld a,h\",\"ld a,l\",\"ld a,(hl)\",\"ld a,a\",\"add a,b\",\"add a,c\",\"add a,d\",\"add a,e\",\"add a,h\",\"add a,l\",\"add a,(hl)\",\"add a,a\",\"adc a,b\",\"adc a,c\",\"adc a,d\",\"adc a,e\",\"adc a,h\",\"adc a,l\",\"adc a,(hl)\",\"adc a,a\",\"sub b\",\"sub c\",\"sub d\",\"sub e\",\"sub h\",\"sub l\",\"sub (hl)\",\"sub a\",\"sbc a,b\",\"sbc a,c\",\"sbc a,d\",\"sbc a,e\",\"sbc a,h\",\"sbc a,l\",\"sbc a,(hl)\",\"sbc a,a\",\"and b\",\"and c\",\"and d\",\"and e\",\"and h\",\"and l\",\"and (hl)\",\"and a\",\"xor b\",\"xor c\",\"xor d\",\"xor e\",\"xor h\",\"xor l\",\"xor (hl)\",\"xor a\",\"or b\",\"or c\",\"or d\",\"or e\",\"or h\",\"or l\",\"or (hl)\",\"or a\",\"cp b\",\"cp c\",\"cp d\",\"cp e\",\"cp h\",\"cp l\",\"cp (hl)\",\"cp a\",\"ret nz\",\"pop bc\",\"jp nz,xx\",\"jp xx\",\"call nz,xx\",\"push bc\",\"add a,x\",\"rst 00h\",\"ret z\",\"ret\",\"jp z,xx\",\"xxBITxx\",\"call z,xx\",\"call xx\",\"adc a,x\",\"rst 08h\",\"ret nc\",\"pop de\",\"jp nc,xx\",\"out (x),a\",\"call nc,xx\",\"push de\",\"sub x\",\"rst 10h\",\"ret c\",\"exx\",\"jp c,xx\",\"in a,(x)\",\"call c,xx\",\"xxIXxx\",\"sbc a,x\",\"rst 18h\",\"ret po\",\"pop hl\",\"jp po,xx\",\"ex (sp),hl\",\"call po,xx\",\"push hl\",\"and x\",\"rst 20h\",\"ret pe\",\"jp (hl)\",\"jp pe,xx\",\"ex de,hl\",\"call pe,xx\",\"xx80xx\",\"xor x\",\"rst 28h\",\"ret p\",\"pop af\",\"jp p,xx\",\"di\",\"call p,xx\",\"push af\",\"or x\",\"rst 30h\",\"ret m\",\"ld sp,hl\",\"jp m,xx\",\"ei\",\"call m,xx\",\"xxIYxx\",\"cp x\",\"rst 38h\"];\nconst Z80_OPS_ED = [\"in b,(c)\",\"out (c),b\",\"sbc hl,bc\",\"ld (xx),bc\",\"neg\",\"retn\",\"im 0\",\"ld i,a\",\"in c,(c)\",\"out (c),c\",\"adc hl,bc\",\"ld bc,(xx)\",\"neg\",\"reti\",\"\",\"ld r,a\",\"in d,(c)\",\"out (c),d\",\"sbc hl,de\",\"ld (xx),de\",\"neg\",\"retn\",\"im 1\",\"ld a,i\",\"in e,(c)\",\"out (c),e\",\"adc hl,de\",\"ld de,(xx)\",\"neg\",\"retn\",\"im 2\",\"ld a,r\",\"in h,(c)\",\"out (c),h\",\"sbc hl,hl\",\"ld (xx),hl\",\"neg\",\"retn\",\"\",\"rrd\",\"in l,(c)\",\"out (c),l\",\"adc hl,hl\",\"ld hl,(xx)\",\"neg\",\"retn\",\"\",\"rld\",\"in f,(c)\",\"out (c),f\",\"sbc hl,sp\",\"ld (xx),sp\",\"neg\",\"retn\",\"\",\"\",\"in a,(c)\",\"out (c),a\",\"adc hl,sp\",\"ld sp,(xx)\",\"neg\",\"reti\",\"\",\"\",\"ldi\",\"cpi\",\"ini\",\"outi\",\"\",\"\",\"\",\"\",\"ldd\",\"cpd\",\"ind\",\"outd\",\"\",\"\",\"\",\"\",\"ldir\",\"cpir\",\"inir\",\"otir\",\"\",\"\",\"\",\"\",\"lddr\",\"cpdr\",\"indr\",\"otdr\",\"\",\"\",\"\",\"\"];\nconst Z80_OPS_CB = [\"rlc b\",\"rlc c\",\"rlc d\",\"rlc e\",\"rlc h\",\"rlc l\",\"rlc (hl)\",\"rlc a\",\"rrc b\",\"rrc c\",\"rrc d\",\"rrc e\",\"rrc h\",\"rrc l\",\"rrc (hl)\",\"rrc a\",\"rl b\",\"rl c\",\"rl d\",\"rl e\",\"rl h\",\"rl l\",\"rl (hl)\",\"rl a\",\"rr b\",\"rr c\",\"rr d\",\"rr e\",\"rr h\",\"rr l\",\"rr (hl)\",\"rr a\",\"sla b\",\"sla c\",\"sla d\",\"sla e\",\"sla h\",\"sla l\",\"sla (hl)\",\"sla a\",\"sra b\",\"sra c\",\"sra d\",\"sra e\",\"sra h\",\"sra l\",\"sra (hl)\",\"sra a\",\"sll b\",\"sll c\",\"sll d\",\"sll e\",\"sll h\",\"sll l\",\"sll (hl)\",\"sll a\",\"srl b\",\"srl c\",\"srl d\",\"srl e\",\"srl h\",\"srl l\",\"srl (hl)\",\"srl a\",\"bit 0,b\",\"bit 0,c\",\"bit 0,d\",\"bit 0,e\",\"bit 0,h\",\"bit 0,l\",\"bit 0,(hl)\",\"bit 0,a\",\"bit 1,b\",\"bit 1,c\",\"bit 1,d\",\"bit 1,e\",\"bit 1,h\",\"bit 1,l\",\"bit 1,(hl)\",\"bit 1,a\",\"bit 2,b\",\"bit 2,c\",\"bit 2,d\",\"bit 2,e\",\"bit 2,h\",\"bit 2,l\",\"bit 2,(hl)\",\"bit 2,a\",\"bit 3,b\",\"bit 3,c\",\"bit 3,d\",\"bit 3,e\",\"bit 3,h\",\"bit 3,l\",\"bit 3,(hl)\",\"bit 3,a\",\"bit 4,b\",\"bit 4,c\",\"bit 4,d\",\"bit 4,e\",\"bit 4,h\",\"bit 4,l\",\"bit 4,(hl)\",\"bit 4,a\",\"bit 5,b\",\"bit 5,c\",\"bit 5,d\",\"bit 5,e\",\"bit 5,h\",\"bit 5,l\",\"bit 5,(hl)\",\"bit 5,a\",\"bit 6,b\",\"bit 6,c\",\"bit 6,d\",\"bit 6,e\",\"bit 6,h\",\"bit 6,l\",\"bit 6,(hl)\",\"bit 6,a\",\"bit 7,b\",\"bit 7,c\",\"bit 7,d\",\"bit 7,e\",\"bit 7,h\",\"bit 7,l\",\"bit 7,(hl)\",\"bit 7,a\",\"res 0,b\",\"res 0,c\",\"res 0,d\",\"res 0,e\",\"res 0,h\",\"res 0,l\",\"res 0,(hl)\",\"res 0,a\",\"res 1,b\",\"res 1,c\",\"res 1,d\",\"res 1,e\",\"res 1,h\",\"res 1,l\",\"res 1,(hl)\",\"res 1,a\",\"res 2,b\",\"res 2,c\",\"res 2,d\",\"res 2,e\",\"res 2,h\",\"res 2,l\",\"res 2,(hl)\",\"res 2,a\",\"res 3,b\",\"res 3,c\",\"res 3,d\",\"res 3,e\",\"res 3,h\",\"res 3,l\",\"res 3,(hl)\",\"res 3,a\",\"res 4,b\",\"res 4,c\",\"res 4,d\",\"res 4,e\",\"res 4,h\",\"res 4,l\",\"res 4,(hl)\",\"res 4,a\",\"res 5,b\",\"res 5,c\",\"res 5,d\",\"res 5,e\",\"res 5,h\",\"res 5,l\",\"res 5,(hl)\",\"res 5,a\",\"res 6,b\",\"res 6,c\",\"res 6,d\",\"res 6,e\",\"res 6,h\",\"res 6,l\",\"res 6,(hl)\",\"res 6,a\",\"res 7,b\",\"res 7,c\",\"res 7,d\",\"res 7,e\",\"res 7,h\",\"res 7,l\",\"res 7,(hl)\",\"res 7,a\",\"set 0,b\",\"set 0,c\",\"set 0,d\",\"set 0,e\",\"set 0,h\",\"set 0,l\",\"set 0,(hl)\",\"set 0,a\",\"set 1,b\",\"set 1,c\",\"set 1,d\",\"set 1,e\",\"set 1,h\",\"set 1,l\",\"set 1,(hl)\",\"set 1,a\",\"set 2,b\",\"set 2,c\",\"set 2,d\",\"set 2,e\",\"set 2,h\",\"set 2,l\",\"set 2,(hl)\",\"set 2,a\",\"set 3,b\",\"set 3,c\",\"set 3,d\",\"set 3,e\",\"set 3,h\",\"set 3,l\",\"set 3,(hl)\",\"set 3,a\",\"set 4,b\",\"set 4,c\",\"set 4,d\",\"set 4,e\",\"set 4,h\",\"set 4,l\",\"set 4,(hl)\",\"set 4,a\",\"set 5,b\",\"set 5,c\",\"set 5,d\",\"set 5,e\",\"set 5,h\",\"set 5,l\",\"set 5,(hl)\",\"set 5,a\",\"set 6,b\",\"set 6,c\",\"set 6,d\",\"set 6,e\",\"set 6,h\",\"set 6,l\",\"set 6,(hl)\",\"set 6,a\",\"set 7,b\",\"set 7,c\",\"set 7,d\",\"set 7,e\",\"set 7,h\",\"set 7,l\",\"set 7,(hl)\",\"set 7,a\"];\n\nexport function disassembleZ80(pc:number, b0:number, b1:number, b2:number, b3:number) : {line:string, nbytes:number, isaddr:boolean} {\n\n var op,n,am;\n var bytes = [b0,b1,b2,b3];\n var isaddr = false;\n n=1;\n switch (b0) {\n case 0xcb:\n am = Z80_OPS_CB[b1];\n n++;\n break;\n case 0xed:\n if (b1 >= 0x40 && b1 <= 0x7f) am = Z80_OPS_ED[b1 - 0x40];\n if (b1 >= 0xa0 && b1 <= 0xbf) am = Z80_OPS_ED[b1 - 0xa0 + 0x40];\n n++;\n break;\n case 0xdd:\n case 0xfd:\n var ireg = (b0 == 0xdd) ? 'ix' : 'iy';\n if (b1 == 0xcb) {\n // swap the 3rd and 4th bytes [$dd $cb displacement opcode]\n am = Z80_OPS_CB[b3];\n bytes[2] = b3;\n bytes[3] = b2;\n n++;\n } else {\n am = Z80_OPS[b1];\n }\n am = am.replace(/[(]hl[)]/, '('+ireg+'+x)');\n am = am.replace(/\\bhl\\b/, ireg);\n n++;\n break;\n default:\n am = Z80_OPS[b0];\n break;\n }\n if (!am || !am.length) am = \"??\";\n if (/\\bxx\\b/.test(am)) {\n am = am.replace(/\\bxx\\b/,'$'+hex(bytes[n]+(bytes[n+1]<<8), 4));\n n += 2;\n isaddr = true;\n } else if (/\\bx\\b/.test(am)) {\n if (am.startsWith('j')) {\n var offset = (b1 < 0x80) ? (pc+2+b1) : (pc+2-(256-b1));\n offset &= 0xffff;\n am = am.replace(/\\bx\\b/,'$'+hex(offset, 4));\n isaddr = true;\n } else {\n am = am.replace(/\\bx\\b/,'$'+hex(bytes[n], 2));\n }\n n += 1;\n }\n return {line:am.toUpperCase(), nbytes:n, isaddr:isaddr};\n};\n", "\nimport { WasmFs } from \"@wasmer/wasmfs\";\nimport { CpuState, EmuState } from \"./baseplatform\";\nimport { CPU, SampledAudioSink, ProbeAll, NullProbe } from \"./devices\";\nimport { EmuHalt } from \"./emu\";\n\n// WASM Support\n// TODO: detangle from c64\n\nexport abstract class BaseWASMMachine {\n prefix : string;\n instance : WebAssembly.Instance;\n exports : any;\n sys : number;\n pixel_dest : Uint32Array;\n pixel_src : Uint32Array;\n stateptr : number;\n statearr : Uint8Array;\n cpustateptr : number;\n cpustatearr : Uint8Array;\n ctrlstateptr : number;\n ctrlstatearr : Uint8Array;\n cpu : CPU;\n romptr : number;\n romlen : number;\n romarr : Uint8Array;\n biosptr : number;\n biosarr : Uint8Array;\n audio : SampledAudioSink;\n audioarr : Float32Array;\n probe : ProbeAll;\n maxROMSize : number = 0x40000;\n\n abstract getCPUState() : CpuState;\n abstract saveState() : EmuState;\n abstract loadState(state: EmuState);\n\n constructor(prefix: string) {\n this.prefix = prefix;\n var self = this;\n this.cpu = {\n getPC: self.getPC.bind(self),\n getSP: self.getSP.bind(self),\n isStable: self.isStable.bind(self),\n reset: self.reset.bind(self),\n saveState: () => {\n return self.getCPUState();\n },\n loadState: () => {\n console.log(\"loadState not implemented\")\n },\n connectMemoryBus() {\n console.log(\"connectMemoryBus not implemented\")\n },\n }\n }\n getImports(wmod: WebAssembly.Module) {\n return {};\n }\n async fetchWASM() {\n var wasmResponse = await fetch('res/'+this.prefix+'.wasm');\n if (wasmResponse.status == 200 || (wasmResponse as any as Blob).size) {\n var wasmBinary = await wasmResponse.arrayBuffer();\n var wasmCompiled = await WebAssembly.compile(wasmBinary);\n var wasmResult = await WebAssembly.instantiate(wasmCompiled, this.getImports(wasmCompiled));\n this.instance = wasmResult;\n this.exports = wasmResult.exports;\n } else throw new Error('could not load WASM file');\n }\n async fetchBIOS() {\n var biosResponse = await fetch('res/'+this.prefix+'.bios');\n if (biosResponse.status == 200 || (biosResponse as any as Blob).size) {\n var biosBinary = await biosResponse.arrayBuffer();\n this.biosptr = this.exports.malloc(biosBinary.byteLength);\n this.biosarr = new Uint8Array(this.exports.memory.buffer, this.biosptr, biosBinary.byteLength);\n this.loadBIOS(new Uint8Array(biosBinary));\n } else throw new Error('could not load BIOS file');\n }\n async initWASM() {\n // init machine instance\n this.sys = this.exports.machine_init(this.biosptr);\n let statesize = this.exports.machine_get_state_size();\n this.stateptr = this.exports.malloc(statesize);\n let ctrlstatesize = this.exports.machine_get_controls_state_size();\n this.ctrlstateptr = this.exports.malloc(ctrlstatesize);\n let cpustatesize = this.exports.machine_get_cpu_state_size();\n this.cpustateptr = this.exports.malloc(cpustatesize);\n this.romptr = this.exports.malloc(this.maxROMSize);\n // create state buffers\n // must do this after allocating memory (and everytime we grow memory?)\n this.statearr = new Uint8Array(this.exports.memory.buffer, this.stateptr, statesize);\n this.ctrlstatearr = new Uint8Array(this.exports.memory.buffer, this.ctrlstateptr, ctrlstatesize);\n this.cpustatearr = new Uint8Array(this.exports.memory.buffer, this.cpustateptr, cpustatesize);\n // create audio buffer\n let sampbufsize = 4096*4;\n this.audioarr = new Float32Array(this.exports.memory.buffer, this.exports.machine_get_sample_buffer(), sampbufsize);\n // create ROM buffer\n this.romarr = new Uint8Array(this.exports.memory.buffer, this.romptr, this.maxROMSize);\n // enable c64 joystick map to arrow keys (TODO)\n //this.exports.c64_set_joystick_type(this.sys, 1);\n console.log('machine_init', this.sys, statesize, ctrlstatesize, cpustatesize, sampbufsize);\n }\n async loadWASM() {\n await this.fetchWASM();\n this.exports.memory.grow(96); // TODO: need more when probing?\n await this.fetchBIOS();\n await this.initWASM();\n }\n getPC() : number {\n return this.exports.machine_cpu_get_pc(this.sys);\n }\n getSP() : number {\n return this.exports.machine_cpu_get_sp(this.sys);\n }\n isStable() : boolean {\n return this.exports.machine_cpu_is_stable(this.sys);\n }\n loadROM(rom: Uint8Array) {\n if (rom.length > this.maxROMSize) throw new EmuHalt(`Rom size too big: ${rom.length} bytes`);\n this.romarr.set(rom);\n this.romlen = rom.length;\n console.log('load rom', rom.length, 'bytes');\n this.reset(); // TODO?\n }\n // TODO: can't load after machine_init\n loadBIOS(srcArray: Uint8Array) {\n this.biosarr.set(srcArray);\n }\n reset() {\n this.exports.machine_reset(this.sys);\n }\n /* TODO: we don't need this because c64_exec does this?\n pollControls() {\n this.exports.machine_start_frame(this.sys);\n }\n */\n read(address: number) : number {\n return this.exports.machine_mem_read(this.sys, address & 0xffff);\n }\n readConst(address: number) : number {\n return this.exports.machine_mem_read(this.sys, address & 0xffff);\n }\n write(address: number, value: number) : void {\n this.exports.machine_mem_write(this.sys, address & 0xffff, value & 0xff);\n }\n getAudioParams() {\n return {sampleRate:44100, stereo:false};\n }\n videoOffsetBytes = 0;\n connectVideo(pixels:Uint32Array) : void {\n this.pixel_dest = pixels;\n var pixbuf = this.exports.machine_get_pixel_buffer(this.sys); // save video pointer\n console.log('connectVideo', pixbuf, pixels.length);\n this.pixel_src = new Uint32Array(this.exports.memory.buffer, pixbuf+this.videoOffsetBytes, pixels.length);\n }\n syncVideo() {\n if (this.exports.machine_update_video) {\n this.exports.machine_update_video(this.sys);\n }\n if (this.pixel_dest != null) {\n this.pixel_dest.set(this.pixel_src);\n }\n }\n // assume controls buffer is smaller than cpu buffer\n saveControlsState() : any {\n //console.log(1, this.romptr, this.romlen, this.ctrlstateptr, this.romarr.slice(0,4), this.ctrlstatearr.slice(0,4));\n this.exports.machine_save_controls_state(this.sys, this.ctrlstateptr);\n //console.log(2, this.romptr, this.romlen, this.ctrlstateptr, this.romarr.slice(0,4), this.ctrlstatearr.slice(0,4));\n return { controls:this.ctrlstatearr.slice(0) }\n }\n loadControlsState(state) : void {\n this.ctrlstatearr.set(state.controls);\n this.exports.machine_load_controls_state(this.sys, this.ctrlstateptr);\n }\n connectAudio(audio : SampledAudioSink) : void {\n this.audio = audio;\n }\n syncAudio() {\n if (this.audio != null) {\n var n = this.exports.machine_get_sample_count();\n for (var i=0; i<n; i++) {\n this.audio.feedSample(this.audioarr[i], 1);\n }\n }\n }\n // TODO: tick might advance 1 instruction\n advanceFrameClock(trap, cpf:number) : number {\n var i : number;\n if (trap) {\n for (i=0; i<cpf; i++) {\n if (trap()) {\n break;\n }\n this.exports.machine_tick(this.sys);\n }\n } else {\n this.exports.machine_exec(this.sys, cpf);\n i = cpf;\n }\n this.syncVideo();\n this.syncAudio();\n return i;\n }\n copyProbeData() {\n if (this.probe && !(this.probe instanceof NullProbe)) {\n var datalen = this.exports.machine_get_probe_buffer_size();\n var dataaddr = this.exports.machine_get_probe_buffer_address();\n // TODO: more efficient way to put into probe\n var databuf = new Uint32Array(this.exports.memory.buffer, dataaddr, datalen);\n this.probe.logNewFrame(); // TODO: machine should do this\n this.probe.addLogBuffer(databuf);\n }\n }\n connectProbe(probe: ProbeAll): void {\n this.probe = probe;\n }\n getDebugTree() {\n return this.saveState();\n }\n}\n\nlet stub = function() { console.log(arguments); return 0 }\n\nexport abstract class BaseWASIMachine extends BaseWASMMachine {\n m_wasi;\n wasiInstance;\n wasmFs : WasmFs;\n \n constructor(prefix: string) {\n super(prefix);\n }\n getImports(wmod: WebAssembly.Module) {\n var imports = this.wasiInstance.getImports(wmod);\n // TODO: eliminate these imports\n imports.env = {\n system: stub,\n __sys_mkdir: stub,\n __sys_chmod: stub,\n __sys_stat64: stub,\n __sys_unlink: stub,\n __sys_rename: stub,\n __sys_getdents64: stub,\n __sys_getcwd: stub,\n __sys_rmdir: stub,\n emscripten_thread_sleep: stub,\n }\n return imports;\n }\n stdoutWrite(buffer) {\n console.log('>>>', buffer.toString());\n return buffer.length;\n }\n async loadWASM() {\n let WASI = await import('@wasmer/wasi');\n let WasmFs = await import('@wasmer/wasmfs');\n this.wasmFs = new WasmFs.WasmFs();\n let bindings = WASI.WASI.defaultBindings;\n bindings.fs = this.wasmFs.fs;\n bindings.fs.mkdirSync('/tmp');\n bindings.path = bindings.path.default;\n this.wasiInstance = new WASI.WASI({\n preopenDirectories: {'/tmp':'/tmp'},\n env: {},\n args: [],\n bindings: bindings\n });\n this.wasmFs.volume.fds[1].write = this.stdoutWrite.bind(this);\n this.wasmFs.volume.fds[2].write = this.stdoutWrite.bind(this);\n await this.fetchWASM();\n this.wasiInstance.start(this.instance);\n await this.initWASM();\n }\n}\n", "\"use strict\";\n/*\nThe MIT License (MIT)\nCopyright (c) 2014 Martin Maly, http://retrocip.cz, http://www.uelectronics.info,\ntwitter: @uelectronics\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of\nthis software and associated documentation files (the \"Software\"), to deal in\nthe Software without restriction, including without limitation the rights to\nuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\nthe Software, and to permit persons to whom the Software is furnished to do so,\nsubject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\nFOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\nCOPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\nIN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\nCONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\nexport function CPU6809() {\n\nvar ticks;\nvar rA,rB,rX,rY,rU,rS,PC,CC,DP,\nF_CARRY =1,\nF_OVERFLOW =2,\nF_ZERO =4,\nF_NEGATIVE =8,\nF_IRQMASK =16,\nF_HALFCARRY =32,\nF_FIRQMASK =64,\nF_ENTIRE =128,\n\nvecRESET = 0xFFFE,\nvecNMI = 0xFFFC,\nvecSWI = 0xFFFA,\nvecIRQ = 0xFFF8,\nvecFIRQ = 0xFFF6,\nvecSWI2 = 0xFFF4,\nvecSWI3 = 0xFFF2,\n\nT=0;\n\nvar IRQs;\n\nvar byteTo, byteAt;\n\nvar cycles = [\n 6,0,0,6,6,0,6,6,6,6,6,0,6,6,3,6, /* 00-0F */\n 0,0,2,4,0,0,5,9,0,2,3,0,3,2,8,6, /* 10-1F */\n 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, /* 20-2F */\n 4,4,4,4,5,5,5,5,0,5,3,6,9,11,0,19, /* 30-3F */\n 2,0,0,2,2,0,2,2,2,2,2,0,2,2,0,2, /* 40-4F */\n 2,0,0,2,2,0,2,2,2,2,2,0,2,2,0,2, /* 50-5F */\n 6,0,0,6,6,0,6,6,6,6,6,0,6,6,3,6, /* 60-6F */\n 7,0,0,7,7,0,7,7,7,7,7,0,7,7,4,7, /* 70-7F */\n 2,2,2,4,2,2,2,0,2,2,2,2,4,7,3,0, /* 80-8F */\n 4,4,4,6,4,4,4,4,4,4,4,4,6,7,5,5, /* 90-9F */\n 4,4,4,6,4,4,4,4,4,4,4,4,6,7,5,5, /* A0-AF */\n 5,5,5,7,5,5,5,5,5,5,5,5,7,8,6,6, /* B0-BF */\n 2,2,2,4,2,2,2,0,2,2,2,2,3,0,3,0, /* C0-CF */\n 4,4,4,6,4,4,4,4,4,4,4,4,5,5,5,5, /* D0-DF */\n 4,4,4,6,4,4,4,4,4,4,4,4,5,5,5,5, /* E0-EF */\n 5,5,5,7,5,5,5,5,5,5,5,5,6,6,6,6]; /* F0-FF */\n\n/* Instruction timing for the two-byte opcodes */\nvar cycles2 = [\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 00-0F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 10-1F */\n 0,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, /* 20-2F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,20, /* 30-3F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40-4F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50-5F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 60-6F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70-7F */\n 0,0,0,5,0,0,0,0,0,0,0,0,5,0,4,0, /* 80-8F */\n 0,0,0,7,0,0,0,0,0,0,0,0,7,0,6,6, /* 90-9F */\n 0,0,0,7,0,0,0,0,0,0,0,0,7,0,6,6, /* A0-AF */\n 0,0,0,8,0,0,0,0,0,0,0,0,8,0,7,7, /* B0-BF */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0, /* C0-CF */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,6, /* D0-DF */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,6, /* E0-EF */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,7,7]; /* F0-FF */\n\n/* Negative and zero flags for quicker flag settings */\nvar flagsNZ = [\n 4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 00-0F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 10-1F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 20-2F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 30-3F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40-4F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50-5F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 60-6F */\n 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70-7F */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* 80-8F */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* 90-9F */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* A0-AF */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* B0-BF */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* C0-CF */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* D0-DF */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, /* E0-EF */\n 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]; /* F0-FF */\n\nvar setV8 = function(a,b,r) {CC |= (((a^b^r^(r>>1))&0x80)>>6);};\nvar setV16 = function(a,b,r) {CC |= (((a^b^r^(r>>1))&0x8000)>>14);};\nvar getD = function() {return (rA<<8)+rB;};\nvar setD = function(v) {rA = (v>>8)& 0xff;rB=v&0xff;};\nvar PUSHB = function(b) {\n byteTo(--rS, b & 0xff);\n};\nvar PUSHW = function(b) {\n byteTo(--rS, b & 0xff);\n byteTo(--rS, (b>>8) & 0xff);\n};\n\nvar PUSHBU = function(b) {\n byteTo(--rU, b & 0xff);\n};\nvar PUSHWU = function(b) {\n byteTo(--rU, b & 0xff);\n byteTo(--rU, (b>>8) & 0xff);\n};\nvar PULLB = function() {\n return byteAt(rS++);\n};\nvar PULLW = function() {\n return byteAt(rS++) * 256 + byteAt(rS++);\n};\n\nvar PULLBU = function() {\n return byteAt(rU++);\n};\nvar PULLWU = function() {\n return byteAt(rU++) * 256 + byteAt(rU++);\n};\n\nvar PSHS = function(ucTemp) {\n var i = 0;\n if (ucTemp & 0x80) {PUSHW(PC);i += 2;}\n if (ucTemp & 0x40) {PUSHW(rU);i += 2;}\n if (ucTemp & 0x20){PUSHW(rY);i += 2;}\n if (ucTemp & 0x10){PUSHW(rX);i += 2;}\n if (ucTemp & 0x8){PUSHB(DP); i++;}\n if (ucTemp & 0x4){PUSHB(rB); i++;}\n if (ucTemp & 0x2){PUSHB(rA); i++;}\n if (ucTemp & 0x1){PUSHB(CC); i++;}\n T+=i; //timing\n};\nvar PSHU = function(ucTemp) {\n var i = 0;\n if (ucTemp & 0x80) {PUSHWU(PC);i += 2;}\n if (ucTemp & 0x40) {PUSHWU(rS);i += 2;}\n if (ucTemp & 0x20){PUSHWU(rY);i += 2;}\n if (ucTemp & 0x10){PUSHWU(rX);i += 2;}\n if (ucTemp & 0x8){PUSHBU(DP); i++;}\n if (ucTemp & 0x4){PUSHBU(rB); i++;}\n if (ucTemp & 0x2){PUSHBU(rA); i++;}\n if (ucTemp & 0x1){PUSHBU(CC); i++;}\n T+=i; //timing\n};\nvar PULS = function(ucTemp) {\n var i = 0;\n if (ucTemp & 0x1){CC = PULLB(); i++;}\n if (ucTemp & 0x2){rA = PULLB(); i++;}\n if (ucTemp & 0x4){rB = PULLB(); i++;}\n if (ucTemp & 0x8){DP = PULLB(); i++;}\n if (ucTemp & 0x10){rX = PULLW();i += 2;}\n if (ucTemp & 0x20){rY = PULLW();i += 2;}\n if (ucTemp & 0x40) {rU = PULLW();i += 2;}\n if (ucTemp & 0x80) {PC = PULLW();i += 2;}\n T+=i; //timing\n};\nvar PULU = function(ucTemp) {\n var i = 0;\n if (ucTemp & 0x1){CC = PULLBU(); i++;}\n if (ucTemp & 0x2){rA = PULLBU(); i++;}\n if (ucTemp & 0x4){rB = PULLBU(); i++;}\n if (ucTemp & 0x8){DP = PULLBU(); i++;}\n if (ucTemp & 0x10){rX = PULLWU();i += 2;}\n if (ucTemp & 0x20){rY = PULLWU();i += 2;}\n if (ucTemp & 0x40) {rS = PULLWU();i += 2;}\n if (ucTemp & 0x80) {PC = PULLWU();i += 2;}\n T+=i; //timing\n};\n\n\nvar getPBR = function(ucPostByte) {\n switch(ucPostByte & 0xf) {\n case 0x00: /* D */\n return getD();\n case 0x1: /* X */\n return rX;\n case 0x2: /* Y */\n return rY;\n case 0x3: /* U */\n return rU;\n case 0x4: /* S */\n return rS;\n case 0x5: /* PC */\n return PC;\n case 0x8: /* A */\n return rA;\n case 0x9: /* B */\n return rB;\n case 0xA: /* CC */\n return CC;\n case 0xB: /* DP */\n return DP;\n default: /* illegal */\n return null;\n }\n};\nvar setPBR = function(ucPostByte, v) {\n switch(ucPostByte & 0xf) /* Get destination register */\n {\n case 0x00: /* D */\n setD(v);return;\n case 0x1: /* X */\n rX = v; return;\n case 0x2: /* Y */\n rY = v; return;\n case 0x3: /* U */\n rU = v; return;\n case 0x4: /* S */\n rS = v; return;\n case 0x5: /* PC */\n PC = v; return;\n case 0x8: /* A */\n rA = v; return;\n case 0x9: /* B */\n rB = v; return;\n case 0xA: /* CC */\n CC = v; return;\n case 0xB: /* DP */\n DP = v; return;\n default: /* illegal */\n return;\n }\n};\n\nvar TFREXG = function(ucPostByte, bExchange)\n{\n\n var ucTemp = ucPostByte & 0x88;\n if (ucTemp == 0x80 || ucTemp == 0x08)\n ucTemp = 0; /* PROBLEM! */\n\n if (bExchange)\n {\n ucTemp = getPBR(ucPostByte>>4);\n setPBR(ucPostByte>>4, getPBR(ucPostByte));\n setPBR(ucPostByte, ucTemp);\n }\n else /* Transfer */ {\n setPBR(ucPostByte, getPBR(ucPostByte>>4));\n }\n} ;\n\nvar signed = function(x) {\n return (x>127)?(x-256):x;\n};\nvar signed16 = function(x) {\n return (x>32767)?(x-65536):x;\n};\n\nvar fetch = function() {\n var v = byteAt(PC++);\n PC &= 0xffff;\n return v;\n};\nvar fetch16 = function() {\n var v1 = byteAt(PC++);\n PC &= 0xffff;\n var v2 = byteAt(PC++);\n PC &= 0xffff;\n return v1*256+v2;\n};\n\nvar ReadWord = function(addr) {\n var v1 = byteAt(addr++);\n addr &= 0xffff;\n var v2 = byteAt(addr++);\n addr &= 0xffff;\n return v1*256+v2;\n};\nvar WriteWord = function(addr,v) {\n byteTo(addr++,(v>>8)&0xff);\n addr &= 0xffff;\n byteTo(addr,v&0xff);\n};\n\nvar PostByte = function() {\n var pb = fetch();\n var preg;\n switch (pb & 0x60) {\n case 0:\n preg = rX; break;\n case 0x20:\n preg = rY; break;\n case 0x40:\n preg = rU; break;\n case 0x60:\n preg = rS; break;\n }\n\n var xchg = null;\n var addr = null;\n var sTemp;\n\n if (pb & 0x80) /* Complex stuff */\n {\n switch (pb & 0x0f)\n {\n case 0: /* EA = ,reg+ */\n addr = preg;\n xchg = preg + 1;\n T += 2;\n break;\n case 1: /* EA = ,reg++ */\n addr = preg;\n xchg = preg + 2;\n T += 3;\n break;\n case 2: /* EA = ,-reg */\n xchg = preg - 1;\n addr = xchg;\n T += 2;\n break;\n case 3: /* EA = ,--reg */\n xchg = preg - 2;\n addr = xchg;\n T += 3;\n break;\n case 4: /* EA = ,reg */\n addr = preg;\n break;\n case 5: /* EA = ,reg + B */\n //usAddr = *pReg + (signed short)(signed char)regs->ucRegB;\n addr = preg + signed(rB);\n T += 1;\n break;\n case 6: /* EA = ,reg + A */\n addr = preg + signed(rA);\n T += 1;\n break;\n case 7: /* illegal */\n addr = 0;\n break;\n case 8: /* EA = ,reg + 8-bit offset */\n addr = preg + signed(fetch());\n T += 1;\n break;\n case 9: /* EA = ,reg + 16-bit offset */\n addr = preg + signed16(fetch16());\n T += 4;\n break;\n case 0xA: /* illegal */\n addr = 0;\n break;\n case 0xB: /* EA = ,reg + D */\n T += 4;\n addr = preg + getD();\n break;\n case 0xC: /* EA = PC + 8-bit offset */\n sTemp = signed(fetch());\n addr = PC + sTemp;\n T += 1;\n break;\n case 0xD: /* EA = PC + 16-bit offset */\n sTemp = signed16(fetch16());\n addr = PC + sTemp;\n T += 5;\n break;\n case 0xe: /* Illegal */\n addr = 0;\n break;\n case 0xF: /* EA = [,address] */\n T += 5;\n addr = fetch16();\n break;\n } /* switch */\n\n addr &= 0xffff;\n\n if (pb & 0x10) /* Indirect addressing */\n {\n addr = byteAt(addr)*256+byteAt((addr+1) & 0xffff);\n T += 3;\n }\n }\n else /* Just a 5 bit signed offset + register */\n {\n var sByte = pb & 0x1f;\n if (sByte > 15) /* Two's complement 5-bit value */\n sByte -= 32;\n addr = preg + sByte;\n T += 1;\n }\n\n if (xchg!==null) {\n switch (pb & 0x60) {\n case 0:\n rX = xchg; break;\n case 0x20:\n rY = xchg; break;\n case 0x40:\n rU = xchg; break;\n case 0x60:\n rS = xchg; break;\n }\n\n }\n\n return addr & 0xffff; /* Return the effective address */\n};\n\nvar flagsNZ16 = function(word) {\n CC &= ~(F_ZERO | F_NEGATIVE);\n if (word===0) CC |= F_ZERO;\n if (word & 0x8000) CC |= F_NEGATIVE;\n};\n\n// ============= Operations\n\nvar oINC = function(b) {\n b++;\n b &= 0xff;\n CC &= ~(F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[b];\n if (b === 0 || b == 0x80) CC |= F_OVERFLOW;\n return b;\n};\nvar oDEC = function(b) {\n b--;\n b &= 0xff;\n CC &= ~(F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[b];\n if (b === 0x7f || b == 0xff) CC |= F_OVERFLOW;\n return b;\n};\nvar oSUB = function(b,v) {\n var temp = b-v;\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[temp & 0xff];\n if (temp&0x100) CC|=F_CARRY;\n setV8(b,v,temp);\n return temp&0xff;\n};\nvar oSUB16 = function(b,v) {\n var temp = b-v;\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n if ((temp&0xffff)===0) CC|=F_ZERO;\n if (temp&0x8000) CC|=F_NEGATIVE;\n if (temp&0x10000) CC|=F_CARRY;\n setV16(b,v,temp);\n return temp&0xffff;\n};\nvar oADD = function(b,v) {\n var temp = b+v;\n //temp &= 0xff;\n CC &= ~(F_HALFCARRY | F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[temp & 0xff];\n if (temp&0x100) CC|=F_CARRY;\n setV8(b,v,temp);\n if ((temp ^ b ^ v)&0x10) CC |= F_HALFCARRY;\n return temp&0xff;\n};\nvar oADD16 = function(b,v) {\n var temp = b+v;\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n if ((temp&0xffff)===0) CC|=F_ZERO;\n if (temp&0x8000) CC|=F_NEGATIVE;\n if (temp&0x10000) CC|=F_CARRY;\n setV16(b,v,temp);\n return temp&0xffff;\n};\nvar oADC = function(b,v) {\n var temp = b+v+(CC & F_CARRY);\n //temp &= 0xff;\n CC &= ~(F_HALFCARRY | F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[temp & 0xff];\n if (temp&0x100) CC|=F_CARRY;\n setV8(b,v,temp);\n if ((temp ^ b ^ v)&0x10) CC |= F_HALFCARRY;\n return temp&0xff;\n};\nvar oSBC = function(b,v) {\n var temp = b-v-(CC & F_CARRY);\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[temp & 0xff];\n if (temp&0x100) CC|=F_CARRY;\n setV8(b,v,temp);\n return temp&0xff;\n};\nvar oCMP = function(b,v) {\n var temp = b-v;\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n CC |= flagsNZ[temp & 0xff];\n if (temp&0x100) CC|=F_CARRY;\n setV8(b,v,temp);\n return;\n};\nvar oCMP16 = function(b,v) {\n var temp = b-v;\n //temp &= 0xff;\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n if ((temp&0xffff)===0) CC|=F_ZERO;\n if (temp&0x8000) CC|=F_NEGATIVE;\n if (temp&0x10000) CC|=F_CARRY;\n setV16(b,v,temp);\n return;\n};\n\nvar oNEG = function(b) {\n CC &= ~(F_CARRY | F_ZERO | F_OVERFLOW | F_NEGATIVE);\n if (b == 0x80)\n CC |= F_OVERFLOW;\n b = ((~b)&0xff) + 1;\n if (b === 0) CC |= F_ZERO;\n if (b & 0x80) CC |= F_NEGATIVE | F_CARRY;\n return b;\n};\n\nvar oLSR = function(b) {\n CC &= ~(F_ZERO | F_CARRY | F_NEGATIVE);\n if (b & 0x01) CC |= F_CARRY;\n b >>= 1;\n if (b === 0) CC |= F_ZERO;\n return b & 0xff;\n};\nvar oASR = function(b) {\n CC &= ~(F_ZERO | F_CARRY | F_NEGATIVE);\n if (b & 0x01) CC |= F_CARRY;\n b = (b & 0x80) | (b>>1);\n CC |= flagsNZ[b];\n return b;\n};\nvar oASL = function(b) {\n var temp = b;\n CC &= ~(F_ZERO | F_CARRY | F_NEGATIVE | F_OVERFLOW);\n if (b & 0x80) CC |= F_CARRY;\n b <<= 1;\n CC |= flagsNZ[b];\n if ((b ^ temp) & 0x80) CC|=F_OVERFLOW;\n return b;\n};\nvar oROL = function(b) {\n var temp = b;\n var oldc = CC&F_CARRY;\n CC &= ~(F_ZERO | F_CARRY | F_NEGATIVE | F_OVERFLOW);\n if (b & 0x80) CC |= F_CARRY;\n b = b<<1 | oldc;\n CC |= flagsNZ[b];\n if ((b ^ temp) & 0x80) CC|=F_OVERFLOW;\n return b;\n};\nvar oROR = function(b) {\n var oldc = CC&F_CARRY;\n CC &= ~(F_ZERO | F_CARRY | F_NEGATIVE);\n if (b & 0x01) CC |= F_CARRY;\n b = b>>1 | oldc<<7;\n CC |= flagsNZ[b];\n// if ((b ^ temp) & 0x80) CC|=F_OVERFLOW;\n return b;\n};\n\nvar oEOR = function(b,v) {\n CC &= ~(F_ZERO | F_NEGATIVE | F_OVERFLOW);\n b ^= v;\n CC |= flagsNZ[b];\n return b;\n};\nvar oOR = function(b,v) {\n CC &= ~(F_ZERO | F_NEGATIVE | F_OVERFLOW);\n b |= v;\n CC |= flagsNZ[b];\n return b;\n};\nvar oAND = function(b,v) {\n CC &= ~(F_ZERO | F_NEGATIVE | F_OVERFLOW);\n b &= v;\n CC |= flagsNZ[b];\n return b;\n};\nvar oCOM = function(b) {\n CC &= ~(F_ZERO | F_NEGATIVE | F_OVERFLOW);\n b ^= 0xff;\n CC |= flagsNZ[b];\n CC |= F_CARRY;\n return b;\n};\n\n//----common\nvar dpadd = function() {\n //direct page + 8bit index\n return DP*256 + fetch();\n};\n\nvar step = function() {\n var oldT = T;\n\n var addr = null;\n var pb = null;\n\n var oldPC = PC;\n var opcode = fetch();\n T+=cycles[opcode];\n switch (opcode) {\n case 0x00: //NEG DP\n addr = dpadd();\n byteTo(addr, oNEG(byteAt(addr)));\n break;\n case 0x03: //COM DP\n addr = dpadd();\n byteTo(addr, oCOM(byteAt(addr)));\n break;\n case 0x04: //LSR DP\n addr = dpadd();\n byteTo(addr, oLSR(byteAt(addr)));\n break;\n case 0x06: //ROR DP\n addr = dpadd();\n byteTo(addr, oROR(byteAt(addr)));\n break;\n case 0x07: //ASR DP\n addr = dpadd();\n byteTo(addr, oASR(byteAt(addr)));\n break;\n case 0x08: //ASL DP\n addr = dpadd();\n byteTo(addr, oASL(byteAt(addr)));\n break;\n case 0x09: //ROL DP\n addr = dpadd();\n byteTo(addr, oROL(byteAt(addr)));\n break;\n\n case 0x0A: //DEC DP\n addr = dpadd();\n byteTo(addr, oDEC(byteAt(addr)));\n break;\n case 0x0C: //INC DP\n addr = dpadd();\n byteTo(addr, oINC(byteAt(addr)));\n break;\n\n case 0x0D: //TST DP\n addr = dpadd();\n pb = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[pb];\n break;\n\n case 0x0E: //JMP DP\n addr = dpadd();\n PC = addr;\n break;\n case 0x0F: //CLR DP\n addr = dpadd();\n byteTo(addr,0);\n CC&=~(F_CARRY|F_NEGATIVE|F_OVERFLOW);\n CC |= F_ZERO;\n break;\n\n case 0x12: //NOP\n break;\n case 0x13: //SYNC\n break;\n case 0x16: //LBRA relative\n addr = signed16(fetch16());\n PC += addr;\n break;\n case 0x17: //LBSR relative\n addr = signed16(fetch16());\n PUSHW(PC);\n PC += addr;\n break;\n case 0x19: //DAA\n var cf = 0;\n var nhi = rA & 0xf0, nlo = rA & 0x0f;\n if( nlo>0x09 || CC & 0x20 ) cf |= 0x06;\n if( nhi>0x80 && nlo>0x09 ) cf |= 0x60;\n if( nhi>0x90 || CC & 0x01 ) cf |= 0x60;\n addr = cf + rA;\n CC &= ~(F_CARRY | F_NEGATIVE | F_ZERO | F_OVERFLOW);\n if (addr & 0x100)\n CC |= F_CARRY;\n rA = addr & 0xff;\n CC |= flagsNZ[rA];\n break;\n case 0x1A: //ORCC\n CC |= fetch();\n break;\n case 0x1C: //ANDCC\n CC &= fetch();\n break;\n case 0x1D: //SEX\n rA = (rB & 0x80)?0xff:0;\n flagsNZ16(getD());\n CC &= ~F_OVERFLOW;\n break;\n case 0x1E: //EXG\n pb = fetch();\n TFREXG(pb,true);\n break;\n case 0x1F: //EXG\n pb = fetch();\n TFREXG(pb,false);\n break;\n\n case 0x20: //BRA\n addr = signed(fetch());\n PC += addr;\n break;\n case 0x21: //BRN\n addr = signed(fetch());\n break;\n case 0x22: //BHI\n addr = signed(fetch());\n if (!(CC&(F_CARRY | F_ZERO))) PC += addr;\n break;\n case 0x23: //BLS\n addr = signed(fetch());\n if (CC&(F_CARRY | F_ZERO)) PC += addr;\n break;\n case 0x24: //BCC\n addr = signed(fetch());\n if (!(CC&F_CARRY)) PC += addr;\n break;\n case 0x25: //BCS\n addr = signed(fetch());\n if (CC&F_CARRY) PC += addr;\n break;\n case 0x26: //BNE\n addr = signed(fetch());\n if (!(CC&F_ZERO)) PC += addr;\n break;\n case 0x27: //BEQ\n addr = signed(fetch());\n if (CC&F_ZERO) PC += addr;\n break;\n case 0x28: //BVC\n addr = signed(fetch());\n if (!(CC&F_OVERFLOW)) PC += addr;\n break;\n case 0x29: //BVS\n addr = signed(fetch());\n if (CC&F_OVERFLOW) PC += addr;\n break;\n case 0x2A: //BPL\n addr = signed(fetch());\n if (!(CC&F_NEGATIVE)) PC += addr;\n break;\n case 0x2B: //BMI\n addr = signed(fetch());\n if (CC&F_NEGATIVE) PC += addr;\n break;\n case 0x2C: //BGE\n addr = signed(fetch());\n if (!((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2))) PC += addr;\n break;\n case 0x2D: //BLT\n addr = signed(fetch());\n if ((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2)) PC += addr;\n break;\n case 0x2E: //BGT\n addr = signed(fetch());\n if (!((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2) || (CC&F_ZERO))) PC += addr;\n break;\n case 0x2F: //BLE\n addr = signed(fetch());\n if ((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2) || (CC&F_ZERO)) PC += addr;\n break;\n\n case 0x30: //LEAX\n rX = PostByte();\n if (rX===0) CC|=F_ZERO; else CC&=~F_ZERO;\n break;\n case 0x31: //LEAY\n rY = PostByte();\n if (rY===0) CC|=F_ZERO; else CC&=~F_ZERO;\n break;\n case 0x32: //LEAS\n rS = PostByte();\n break;\n case 0x33: //LEAU\n rU = PostByte();\n break;\n\n case 0x34: //PSHS\n PSHS(fetch());\n break;\n case 0x35: //PULS\n PULS(fetch());\n break;\n case 0x36: //PSHU\n PSHU(fetch());\n break;\n case 0x37: //PULU\n PULU(fetch());\n break;\n case 0x39: //RTS\n PC = PULLW();\n break;\n case 0x3A: //ABX\n rX += rB;\n break;\n case 0x3B: //RTI\n CC = PULLB();\n if (CC & F_ENTIRE) {\n T+=9;\n rA = PULLB();\n rB = PULLB();\n DP = PULLB();\n rX = PULLW();\n rY = PULLW();\n rU = PULLW();\n }\n PC = PULLW();\n break;\n case 0x3C: //CWAI **todo\n CC &= fetch();\n break;\n case 0x3D: //MUL\n addr = rA * rB;\n if (addr===0) CC|=F_ZERO; else CC&=~F_ZERO;\n if (addr&0x80) CC|=F_CARRY; else CC&=~F_CARRY;\n setD(addr);\n break;\n case 0x3F: //SWI\n CC |= F_ENTIRE;\n PUSHW(PC);\n PUSHW(rU);\n PUSHW(rY);\n PUSHW(rX);\n PUSHB(DP);\n PUSHB(rB);\n PUSHB(rA);\n PUSHB(CC);\n CC |= F_IRQMASK | F_FIRQMASK;\n PC = ReadWord(vecSWI);\n break;\n\n case 0x40:\n rA = oNEG(rA);\n break;\n case 0x43:\n rA = oCOM(rA);\n break;\n case 0x44:\n rA = oLSR(rA);\n break;\n case 0x46:\n rA = oROR(rA);\n break;\n case 0x47:\n rA = oASR(rA);\n break;\n case 0x48:\n rA = oASL(rA);\n break;\n case 0x49:\n rA = oROL(rA);\n break;\n case 0x4A:\n rA = oDEC(rA);\n break;\n case 0x4C:\n rA = oINC(rA);\n break;\n case 0x4D:\n CC &= ~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0x4F:\n rA = 0;\n CC &= ~(F_NEGATIVE|F_OVERFLOW|F_CARRY);\n CC |= F_ZERO;\n break;\n\n case 0x50:\n rB = oNEG(rB);\n break;\n case 0x53:\n rB = oCOM(rB);\n break;\n case 0x54:\n rB = oLSR(rB);\n break;\n case 0x56:\n rB = oROR(rB);\n break;\n case 0x57:\n rB = oASR(rB);\n break;\n case 0x58:\n rB = oASL(rB);\n break;\n case 0x59:\n rB = oROL(rB);\n break;\n case 0x5A:\n rB = oDEC(rB);\n break;\n case 0x5C:\n rB = oINC(rB);\n break;\n case 0x5D:\n CC &= ~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0x5F:\n rB = 0;\n CC &= ~(F_NEGATIVE|F_OVERFLOW|F_CARRY);\n CC |= F_ZERO;\n break;\n\n case 0x60: //NEG indexed\n addr = PostByte();\n byteTo(addr, oNEG(byteAt(addr)));\n break;\n case 0x63: //COM indexed\n addr = PostByte();\n byteTo(addr, oCOM(byteAt(addr)));\n break;\n case 0x64: //LSR indexed\n addr = PostByte();\n byteTo(addr, oLSR(byteAt(addr)));\n break;\n case 0x66: //ROR indexed\n addr = PostByte();\n byteTo(addr, oROR(byteAt(addr)));\n break;\n case 0x67: //ASR indexed\n addr = PostByte();\n byteTo(addr, oASR(byteAt(addr)));\n break;\n case 0x68: //ASL indexed\n addr = PostByte();\n byteTo(addr, oASL(byteAt(addr)));\n break;\n case 0x69: //ROL indexed\n addr = PostByte();\n byteTo(addr, oROL(byteAt(addr)));\n break;\n\n case 0x6A: //DEC indexed\n addr = PostByte();\n byteTo(addr, oDEC(byteAt(addr)));\n break;\n case 0x6C: //INC indexed\n addr = PostByte();\n byteTo(addr, oINC(byteAt(addr)));\n break;\n\n case 0x6D: //TST indexed\n addr = PostByte();\n pb = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[pb];\n break;\n\n case 0x6E: //JMP indexed\n addr = PostByte();\n PC = addr;\n break;\n case 0x6F: //CLR indexed\n addr = PostByte();\n byteTo(addr,0);\n CC&=~(F_CARRY|F_NEGATIVE|F_OVERFLOW);\n CC |= F_ZERO;\n break;\n\n\n case 0x70: //NEG extended\n addr = fetch16();\n byteTo(addr, oNEG(byteAt(addr)));\n break;\n case 0x73: //COM extended\n addr = fetch16();\n byteTo(addr, oCOM(byteAt(addr)));\n break;\n case 0x74: //LSR extended\n addr = fetch16();\n byteTo(addr, oLSR(byteAt(addr)));\n break;\n case 0x76: //ROR extended\n addr = fetch16();\n byteTo(addr, oROR(byteAt(addr)));\n break;\n case 0x77: //ASR extended\n addr = fetch16();\n byteTo(addr, oASR(byteAt(addr)));\n break;\n case 0x78: //ASL extended\n addr = fetch16();\n byteTo(addr, oASL(byteAt(addr)));\n break;\n case 0x79: //ROL extended\n addr = fetch16();\n byteTo(addr, oROL(byteAt(addr)));\n break;\n\n case 0x7A: //DEC extended\n addr = fetch16();\n byteTo(addr, oDEC(byteAt(addr)));\n break;\n case 0x7C: //INC extended\n addr = fetch16();\n byteTo(addr, oINC(byteAt(addr)));\n break;\n\n case 0x7D: //TST extended\n addr = fetch16();\n pb = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[pb];\n break;\n\n case 0x7E: //JMP extended\n addr = fetch16();\n PC = addr;\n break;\n case 0x7F: //CLR extended\n addr = fetch16();\n byteTo(addr,0);\n CC&=~(F_CARRY|F_NEGATIVE|F_OVERFLOW);\n CC |= F_ZERO;\n break;\n\n // regs A,X\n\n case 0x80: //SUBA imm\n rA = oSUB(rA, fetch());\n break;\n case 0x81: //CMPA imm\n oCMP(rA, fetch());\n break;\n case 0x82: //SBCA imm\n rA = oSBC(rA, fetch());\n break;\n case 0x83: //SUBD imm\n setD(oSUB16(getD(),fetch16()));\n break;\n case 0x84: //ANDA imm\n rA = oAND(rA, fetch());\n break;\n case 0x85: //BITA imm\n oAND(rA, fetch());\n break;\n case 0x86: //LDA imm\n rA = fetch();\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0x88: //EORA imm\n rA = oEOR(rA, fetch());\n break;\n case 0x89: //ADCA imm\n rA = oADC(rA, fetch());\n break;\n case 0x8A: //ORA imm\n rA = oOR(rA, fetch());\n break;\n case 0x8B: //ADDA imm\n rA = oADD(rA, fetch());\n break;\n case 0x8C: //CMPX imm\n oCMP16(rX, fetch16());\n break;\n\n case 0x8D: //JSR imm\n addr = signed(fetch());\n PUSHW(PC);\n PC+=addr;\n break;\n case 0x8E: //LDX imm\n rX = fetch16();\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n\n\n case 0x90: //SUBA direct\n addr = dpadd();\n rA = oSUB(rA, byteAt(addr));\n break;\n case 0x91: //CMPA direct\n addr = dpadd();\n oCMP(rA, byteAt(addr));\n break;\n case 0x92: //SBCA direct\n addr = dpadd();\n rA = oSBC(rA, byteAt(addr));\n break;\n case 0x93: //SUBD direct\n addr = dpadd();\n setD(oSUB16(getD(),ReadWord(addr)));\n break;\n case 0x94: //ANDA direct\n addr = dpadd();\n rA = oAND(rA, byteAt(addr));\n break;\n case 0x95: //BITA direct\n addr = dpadd();\n oAND(rA, byteAt(addr));\n break;\n case 0x96: //LDA direct\n addr = dpadd();\n rA = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0x97: //STA direct\n addr = dpadd();\n byteTo(addr,rA);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0x98: //EORA direct\n addr = dpadd();\n rA = oEOR(rA, byteAt(addr));\n break;\n case 0x99: //ADCA direct\n addr = dpadd();\n rA = oADC(rA, byteAt(addr));\n break;\n case 0x9A: //ORA direct\n addr = dpadd();\n rA = oOR(rA, byteAt(addr));\n break;\n case 0x9B: //ADDA direct\n addr = dpadd();\n rA = oADD(rA, byteAt(addr));\n break;\n case 0x9C: //CMPX direct\n addr = dpadd();\n oCMP16(rX, ReadWord(addr));\n break;\n\n case 0x9D: //JSR direct\n addr = dpadd();\n PUSHW(PC);\n PC=addr;\n break;\n case 0x9E: //LDX direct\n addr = dpadd();\n rX = ReadWord(addr);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n case 0x9F: //STX direct\n addr = dpadd();\n WriteWord(addr,rX);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n case 0xA0: //SUBA indexed\n addr = PostByte();\n rA = oSUB(rA, byteAt(addr));\n break;\n case 0xA1: //CMPA indexed\n addr = PostByte();\n oCMP(rA, byteAt(addr));\n break;\n case 0xA2: //SBCA indexed\n addr = PostByte();\n rA = oSBC(rA, byteAt(addr));\n break;\n case 0xA3: //SUBD indexed\n addr = PostByte();\n setD(oSUB16(getD(),ReadWord(addr)));\n break;\n case 0xA4: //ANDA indexed\n addr = PostByte();\n rA = oAND(rA, byteAt(addr));\n break;\n case 0xA5: //BITA indexed\n addr = PostByte();\n oAND(rA, byteAt(addr));\n break;\n case 0xA6: //LDA indexed\n addr = PostByte();\n rA = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0xA7: //STA indexed\n addr = PostByte();\n byteTo(addr,rA);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0xA8: //EORA indexed\n addr = PostByte();\n rA = oEOR(rA, byteAt(addr));\n break;\n case 0xA9: //ADCA indexed\n addr = PostByte();\n rA = oADC(rA, byteAt(addr));\n break;\n case 0xAA: //ORA indexed\n addr = PostByte();\n rA = oOR(rA, byteAt(addr));\n break;\n case 0xAB: //ADDA indexed\n addr = PostByte();\n rA = oADD(rA, byteAt(addr));\n break;\n case 0xAC: //CMPX indexed\n addr = PostByte();\n oCMP16(rX, ReadWord(addr));\n break;\n\n case 0xAD: //JSR indexed\n addr = PostByte();\n PUSHW(PC);\n PC=addr;\n break;\n case 0xAE: //LDX indexed\n addr = PostByte();\n rX = ReadWord(addr);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n case 0xAF: //STX indexed\n addr = PostByte();\n WriteWord(addr,rX);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n\n\n case 0xB0: //SUBA extended\n addr = fetch16();\n rA = oSUB(rA, byteAt(addr));\n break;\n case 0xB1: //CMPA extended\n addr = fetch16();\n oCMP(rA, byteAt(addr));\n break;\n case 0xB2: //SBCA extended\n addr = fetch16();\n rA = oSBC(rA, byteAt(addr));\n break;\n case 0xB3: //SUBD extended\n addr = fetch16();\n setD(oSUB16(getD(),ReadWord(addr)));\n break;\n case 0xB4: //ANDA extended\n addr = fetch16();\n rA = oAND(rA, byteAt(addr));\n break;\n case 0xB5: //BITA extended\n addr = fetch16();\n oAND(rA, byteAt(addr));\n break;\n case 0xB6: //LDA extended\n addr = fetch16();\n rA = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0xB7: //STA extended\n addr = fetch16();\n byteTo(addr,rA);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rA];\n break;\n case 0xB8: //EORA extended\n addr = fetch16();\n rA = oEOR(rA, byteAt(addr));\n break;\n case 0xB9: //ADCA extended\n addr = fetch16();\n rA = oADC(rA, byteAt(addr));\n break;\n case 0xBA: //ORA extended\n addr = fetch16();\n rA = oOR(rA, byteAt(addr));\n break;\n case 0xBB: //ADDA extended\n addr = fetch16();\n rA = oADD(rA, byteAt(addr));\n break;\n case 0xBC: //CMPX extended\n addr = fetch16();\n oCMP16(rX, ReadWord(addr));\n break;\n\n case 0xBD: //JSR extended\n addr = fetch16();\n PUSHW(PC);\n PC=addr;\n break;\n case 0xBE: //LDX extended\n addr = fetch16();\n rX = ReadWord(addr);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n case 0xBF: //STX extended\n addr = fetch16();\n WriteWord(addr,rX);\n flagsNZ16(rX);\n CC&=~F_OVERFLOW;\n break;\n\n //Regs B, Y\n\n case 0xC0: //SUBB imm\n rB = oSUB(rB, fetch());\n break;\n case 0xC1: //CMPB imm\n oCMP(rB, fetch());\n break;\n case 0xC2: //SBCB imm\n rB = oSBC(rB, fetch());\n break;\n case 0xC3: //ADDD imm\n setD(oADD16(getD(),fetch16()));\n break;\n case 0xC4: //ANDB imm\n rB = oAND(rB, fetch());\n break;\n case 0xC5: //BITB imm\n oAND(rB, fetch());\n break;\n case 0xC6: //LDB imm\n rB = fetch();\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xC8: //EORB imm\n rB = oEOR(rB, fetch());\n break;\n case 0xC9: //ADCB imm\n rB = oADC(rB, fetch());\n break;\n case 0xCA: //ORB imm\n rB = oOR(rB, fetch());\n break;\n case 0xCB: //ADDB imm\n rB = oADD(rB, fetch());\n break;\n case 0xCC: //LDD imm\n addr = fetch16();\n setD(addr);\n flagsNZ16(addr);\n CC&=~F_OVERFLOW;\n break;\n\n case 0xCE: //LDU imm\n rU = fetch16();\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n\n\n case 0xD0: //SUBB direct\n addr = dpadd();\n rB = oSUB(rB, byteAt(addr));\n break;\n case 0xD1: //CMPB direct\n addr = dpadd();\n oCMP(rB, byteAt(addr));\n break;\n case 0xD2: //SBCB direct\n addr = dpadd();\n rB = oSBC(rB, byteAt(addr));\n break;\n case 0xD3: //ADDD direct\n addr = dpadd();\n setD(oADD16(getD(),ReadWord(addr)));\n break;\n case 0xD4: //ANDB direct\n addr = dpadd();\n rB = oAND(rB, byteAt(addr));\n break;\n case 0xD5: //BITB direct\n addr = dpadd();\n oAND(rB, byteAt(addr));\n break;\n case 0xD6: //LDB direct\n addr = dpadd();\n rB = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xD7: //STB direct\n addr = dpadd();\n byteTo(addr,rB);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xD8: //EORB direct\n addr = dpadd();\n rB = oEOR(rB, byteAt(addr));\n break;\n case 0xD9: //ADCB direct\n addr = dpadd();\n rB = oADC(rB, byteAt(addr));\n break;\n case 0xDA: //ORB direct\n addr = dpadd();\n rB = oOR(rB, byteAt(addr));\n break;\n case 0xDB: //ADDB direct\n addr = dpadd();\n rB = oADD(rB, byteAt(addr));\n break;\n case 0xDC: //LDD direct\n addr = dpadd();\n pb = ReadWord(addr);\n setD(pb);\n flagsNZ16(pb);\n CC&=~F_OVERFLOW;\n break;\n\n case 0xDD: //STD direct\n addr = dpadd();\n WriteWord(addr, getD());\n CC&=~F_OVERFLOW;\n break;\n case 0xDE: //LDU direct\n addr = dpadd();\n rU = ReadWord(addr);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n case 0xDF: //STU direct\n addr = dpadd();\n WriteWord(addr,rU);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n case 0xE0: //SUBB indexed\n addr = PostByte();\n rB = oSUB(rB, byteAt(addr));\n break;\n case 0xE1: //CMPB indexed\n addr = PostByte();\n oCMP(rB, byteAt(addr));\n break;\n case 0xE2: //SBCB indexed\n addr = PostByte();\n rB = oSBC(rB, byteAt(addr));\n break;\n case 0xE3: //ADDD indexed\n addr = PostByte();\n setD(oADD16(getD(),ReadWord(addr)));\n break;\n case 0xE4: //ANDB indexed\n addr = PostByte();\n rB = oAND(rB, byteAt(addr));\n break;\n case 0xE5: //BITB indexed\n addr = PostByte();\n oAND(rB, byteAt(addr));\n break;\n case 0xE6: //LDB indexed\n addr = PostByte();\n rB = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xE7: //STB indexed\n addr = PostByte();\n byteTo(addr,rB);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xE8: //EORB indexed\n addr = PostByte();\n rB = oEOR(rB, byteAt(addr));\n break;\n case 0xE9: //ADCB indexed\n addr = PostByte();\n rB = oADC(rB, byteAt(addr));\n break;\n case 0xEA: //ORB indexed\n addr = PostByte();\n rB = oOR(rB, byteAt(addr));\n break;\n case 0xEB: //ADDB indexed\n addr = PostByte();\n rB = oADD(rB, byteAt(addr));\n break;\n case 0xEC: //LDD indexed\n addr = PostByte();\n pb = ReadWord(addr);\n setD(pb);\n flagsNZ16(pb);\n CC&=~F_OVERFLOW;\n break;\n\n case 0xED: //STD indexed\n addr = PostByte();\n WriteWord(addr, getD());\n CC&=~F_OVERFLOW;\n break;\n case 0xEE: //LDU indexed\n addr = PostByte();\n rU = ReadWord(addr);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n case 0xEF: //STU indexed\n addr = PostByte();\n WriteWord(addr,rU);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n\n\n case 0xF0: //SUBB extended\n addr = fetch16();\n rB = oSUB(rB, byteAt(addr));\n break;\n case 0xF1: //CMPB extended\n addr = fetch16();\n oCMP(rB, byteAt(addr));\n break;\n case 0xF2: //SBCB extended\n addr = fetch16();\n rB = oSBC(rB, byteAt(addr));\n break;\n case 0xF3: //ADDD extended\n addr = fetch16();\n setD(oADD16(getD(),ReadWord(addr)));\n break;\n case 0xF4: //ANDB extended\n addr = fetch16();\n rB = oAND(rB, byteAt(addr));\n break;\n case 0xF5: //BITB extended\n addr = fetch16();\n oAND(rB, byteAt(addr));\n break;\n case 0xF6: //LDB extended\n addr = fetch16();\n rB = byteAt(addr);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xF7: //STB extended\n addr = fetch16();\n byteTo(addr,rB);\n CC&=~(F_ZERO|F_NEGATIVE|F_OVERFLOW);\n CC |= flagsNZ[rB];\n break;\n case 0xF8: //EORB extended\n addr = fetch16();\n rB = oEOR(rB, byteAt(addr));\n break;\n case 0xF9: //ADCB extended\n addr = fetch16();\n rB = oADC(rB, byteAt(addr));\n break;\n case 0xFA: //ORB extended\n addr = fetch16();\n rB = oOR(rB, byteAt(addr));\n break;\n case 0xFB: //ADDB extended\n addr = fetch16();\n rB = oADD(rB, byteAt(addr));\n break;\n case 0xFC: //LDD extended\n addr = fetch16();\n pb = ReadWord(addr);\n setD(pb);\n flagsNZ16(pb);\n CC&=~F_OVERFLOW;\n break;\n\n case 0xFD: //STD extended\n addr = fetch16();\n WriteWord(addr, getD());\n CC&=~F_OVERFLOW;\n break;\n case 0xFE: //LDU extended\n addr = fetch16();\n rU = ReadWord(addr);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n case 0xFF: //STU extended\n addr = fetch16();\n WriteWord(addr,rU);\n flagsNZ16(rU);\n CC&=~F_OVERFLOW;\n break;\n\n // page 1\n case 0x10: //page 1\n {\n opcode = fetch();\n T+=cycles2[opcode];\n switch(opcode) {\n case 0x21: //BRN\n addr = signed16(fetch16());\n break;\n case 0x22: //BHI\n addr = signed16(fetch16());\n if (!(CC&(F_CARRY | F_ZERO))) PC += addr;\n break;\n case 0x23: //BLS\n addr = signed16(fetch16());\n if (CC&(F_CARRY | F_ZERO)) PC += addr;\n break;\n case 0x24: //BCC\n addr = signed16(fetch16());\n if (!(CC&F_CARRY)) PC += addr;\n break;\n case 0x25: //BCS\n addr = signed16(fetch16());\n if (CC&F_CARRY) PC += addr;\n break;\n case 0x26: //BNE\n addr = signed16(fetch16());\n if (!(CC&F_ZERO)) PC += addr;\n break;\n case 0x27: //BEQ\n addr = signed16(fetch16());\n if (CC&F_ZERO) PC += addr;\n break;\n case 0x28: //BVC\n addr = signed16(fetch16());\n if (!(CC&F_OVERFLOW)) PC += addr;\n break;\n case 0x29: //BVS\n addr = signed16(fetch16());\n if (CC&F_OVERFLOW) PC += addr;\n break;\n case 0x2A: //BPL\n addr = signed16(fetch16());\n if (!(CC&F_NEGATIVE)) PC += addr;\n break;\n case 0x2B: //BMI\n addr = signed16(fetch16());\n if (CC&F_NEGATIVE) PC += addr;\n break;\n case 0x2C: //BGE\n addr = signed16(fetch16());\n if (!((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2))) PC += addr;\n break;\n case 0x2D: //BLT\n addr = signed16(fetch16());\n if ((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2)) PC += addr;\n break;\n case 0x2E: //BGT\n addr = signed16(fetch16());\n if (!((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2) || (CC&F_ZERO))) PC += addr;\n break;\n case 0x2F: //BLE\n addr = signed16(fetch16());\n if ((CC&F_NEGATIVE) ^ ((CC&F_OVERFLOW)<<2) || (CC&F_ZERO)) PC += addr;\n break;\n case 0x3f: //SWI2\n CC |= F_ENTIRE;\n PUSHW(PC);\n PUSHW(rU);\n PUSHW(rY);\n PUSHW(rX);\n PUSHB(DP);\n PUSHB(rB);\n PUSHB(rA);\n PUSHB(CC);\n CC |= F_IRQMASK | F_FIRQMASK;\n PC = ReadWord(vecSWI2);\n break;\n case 0x83: //CMPD imm\n oCMP16(getD(),fetch16());\n break;\n case 0x8C: //CMPY imm\n oCMP16(rY,fetch16());\n break;\n case 0x8E: //LDY imm\n rY = fetch16();\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0x93: //CMPD direct\n addr = dpadd();\n oCMP16(getD(),ReadWord(addr));\n break;\n case 0x9C: //CMPY direct\n addr = dpadd();\n oCMP16(rY,ReadWord(addr));\n break;\n case 0x9E: //LDY direct\n addr = dpadd();\n rY = ReadWord(addr);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0x9F: //STY direct\n addr = dpadd();\n WriteWord(addr,rY);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0xA3: //CMPD indexed\n addr = PostByte();\n oCMP16(getD(),ReadWord(addr));\n break;\n case 0xAC: //CMPY indexed\n addr = PostByte();\n oCMP16(rY,ReadWord(addr));\n break;\n case 0xAE: //LDY indexed\n addr = PostByte();\n rY = ReadWord(addr);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0xAF: //STY indexed\n addr = PostByte();\n WriteWord(addr,rY);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0xB3: //CMPD extended\n addr = fetch16();\n oCMP16(getD(),ReadWord(addr));\n break;\n case 0xBC: //CMPY extended\n addr = fetch16();\n oCMP16(rY,ReadWord(addr));\n break;\n case 0xBE: //LDY extended\n addr = fetch16();\n rY = ReadWord(addr);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0xBF: //STY extended\n addr = fetch16();\n WriteWord(addr,rY);\n flagsNZ16(rY);\n CC&=~F_OVERFLOW;\n break;\n case 0xCE: //LDS imm\n rS = fetch16();\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xDE: //LDS direct\n addr = dpadd();\n rS = ReadWord(addr);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xDF: //STS direct\n addr = dpadd();\n WriteWord(addr,rS);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xEE: //LDS indexed\n addr = PostByte();\n rS = ReadWord(addr);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xEF: //STS indexed\n addr = PostByte();\n WriteWord(addr,rS);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xFE: //LDS extended\n addr = fetch16();\n rS = ReadWord(addr);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n case 0xFF: //STS extended\n addr = fetch16();\n WriteWord(addr,rS);\n flagsNZ16(rS);\n CC&=~F_OVERFLOW;\n break;\n }\n }\n break;\n // page 2\n case 0x11: //page 2\n {\n opcode = fetch();\n T+=cycles2[opcode];\n switch(opcode) {\n case 0x3f: //SWI3\n CC |= F_ENTIRE;\n PUSHW(PC);\n PUSHW(rU);\n PUSHW(rY);\n PUSHW(rX);\n PUSHB(DP);\n PUSHB(rB);\n PUSHB(rA);\n PUSHB(CC);\n CC |= F_IRQMASK | F_FIRQMASK;\n PC = ReadWord(vecSWI3);\n break;\n case 0x83: //CMPU imm\n oCMP16(rU, fetch16());\n break;\n case 0x8C: //CMPS imm\n oCMP16(rS, fetch16());\n break;\n case 0x93: //CMPU imm\n addr = dpadd();\n oCMP16(rU, ReadWord(addr));\n break;\n case 0x9C: //CMPS imm\n addr = dpadd();\n oCMP16(rS, ReadWord(addr));\n break;\n case 0xA3: //CMPU imm\n addr = PostByte();\n oCMP16(rU, ReadWord(addr));\n break;\n case 0xAC: //CMPS imm\n addr = PostByte();\n oCMP16(rS, ReadWord(addr));\n break;\n case 0xB3: //CMPU imm\n addr = fetch16();\n oCMP16(rU, ReadWord(addr));\n break;\n case 0xBC: //CMPS imm\n addr = fetch16();\n oCMP16(rS, ReadWord(addr));\n break;\n\n }\n }\n break;\n\n\n }\n\n rA &= 0xff;\n rB &= 0xff;\n CC &= 0xff;\n DP &= 0xff;\n rX &= 0xffff;\n rY &= 0xffff;\n rU &= 0xffff;\n rS &= 0xffff;\n PC &= 0xffff;\n return T-oldT;\n\n};\n\nvar reset = function(){\n PC = ReadWord(vecRESET);\n DP = 0;\n CC |= F_FIRQMASK | F_IRQMASK;\n T=0;\n rA=rB=DP=rX=rY=rU=rS=0;\n};\n\n//---------- Disassembler\n\n/*\nILLEGAL 0\nDIRECT 1\nINHERENT 2\nBRANCH_REL_16 3\nIMMEDIAT_8 4\nBRANCH_REL_8 5\nINDEXED 6\nEXTENDED 7\nIMMEDIAT_16 8\n\nPSHS 10\nPSHU 11\n\nEXG, TFR 20\n*/\nvar ds = [\n[2, 1,\"NEG\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[2, 1,\"COM\"],\n[2, 1,\"LSR\"],\n[1, 0,\"???\"],\n[2, 1,\"ROR\"],\n[2, 1,\"ASR\"],\n[2, 1,\"LSL\"],\n[2, 1,\"ROL\"],\n[2, 1,\"DEC\"],\n[1, 0,\"???\"],\n[2, 1,\"INC\"],\n[2, 1,\"TST\"],\n[2, 1,\"JMP\"],\n[2, 1,\"CLR\"],\n[1, 0,\"Prefix\"],\n[1, 0,\"Prefix\"],\n[1, 2,\"NOP\"],\n[1, 2,\"SYNC\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[3, 3,\"LBRA\"],\n[3, 3,\"LBSR\"],\n[1, 0,\"???\"],\n[1, 2,\"DAA\"],\n[2, 4,\"ORCC\"],\n[1, 0,\"???\"],\n[2, 4,\"ANDCC\"],\n[1, 2,\"SEX\"],\n[2, 20,\"EXG\"],\n[2, 20,\"TFR\"],\n[2, 5,\"BRA\"],\n[2, 5,\"BRN\"],\n[2, 5,\"BHI\"],\n[2, 5,\"BLS\"],\n[2, 5,\"BCC\"],\n[2, 5,\"BCS\"],\n[2, 5,\"BNE\"],\n[2, 5,\"BEQ\"],\n[2, 5,\"BVC\"],\n[2, 5,\"BVS\"],\n[2, 5,\"BPL\"],\n[2, 5,\"BMI\"],\n[2, 5,\"BGE\"],\n[2, 5,\"BLT\"],\n[2, 5,\"BGT\"],\n[2, 5,\"BLE\"],\n[2, 6,\"LEAX\"],\n[2, 6,\"LEAY\"],\n[2, 6,\"LEAS\"],\n[2, 6,\"LEAU\"],\n[2, 10,\"PSHS\"],\n[2, 10,\"PULS\"],\n[2, 11,\"PSHU\"],\n[2, 11,\"PULU\"],\n[1, 0,\"???\"],\n[1, 2,\"RTS\"],\n[1, 2,\"ABX\"],\n[1, 2,\"RTI\"],\n[2, 2,\"CWAI\"],\n[1, 2,\"MUL\"],\n[1, 2,\"RESET\"],\n[1, 2,\"SWI1\"],\n[1, 2,\"NEGA\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[1, 2,\"COMA\"],\n[1, 2,\"LSRA\"],\n[1, 0,\"???\"],\n[1, 2,\"RORA\"],\n[1, 2,\"ASRA\"],\n[1, 2,\"ASLA\"],\n[1, 2,\"ROLA\"],\n[1, 2,\"DECA\"],\n[1, 0,\"???\"],\n[1, 2,\"INCA\"],\n[1, 2,\"TSTA\"],\n[1, 0,\"???\"],\n[1, 2,\"CLRA\"],\n[1, 2,\"NEGB\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[1, 2,\"COMB\"],\n[1, 2,\"LSRB\"],\n[1, 0,\"???\"],\n[1, 2,\"RORB\"],\n[1, 2,\"ASRB\"],\n[1, 2,\"ASLB\"],\n[1, 2,\"ROLB\"],\n[1, 2,\"DECB\"],\n[1, 0,\"???\"],\n[1, 2,\"INCB\"],\n[1, 2,\"TSTB\"],\n[1, 0,\"???\"],\n[1, 2,\"CLRB\"],\n[2, 6,\"NEG\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[2, 6,\"COM\"],\n[2, 6,\"LSR\"],\n[1, 0,\"???\"],\n[2, 6,\"ROR\"],\n[2, 6,\"ASR\"],\n[2, 6,\"LSL\"],\n[2, 6,\"ROL\"],\n[2, 6,\"DEC\"],\n[1, 0,\"???\"],\n[2, 6,\"INC\"],\n[2, 6,\"TST\"],\n[2, 6,\"JMP\"],\n[2, 6,\"CLR\"],\n[3, 7,\"NEG\"],\n[1, 0,\"???\"],\n[1, 0,\"???\"],\n[3, 7,\"COM\"],\n[3, 7,\"LSR\"],\n[1, 0,\"???\"],\n[3, 7,\"ROR\"],\n[3, 7,\"ASR\"],\n[3, 7,\"LSL\"],\n[3, 7,\"ROL\"],\n[3, 7,\"DEC\"],\n[1, 0,\"???\"],\n[3, 7,\"INC\"],\n[3, 7,\"TST\"],\n[3, 7,\"JMP\"],\n[3, 7,\"CLR\"],\n[2, 4,\"SUBA\"],\n[2, 4,\"CMPA\"],\n[2, 4,\"SBCA\"],\n[3, 8,\"SUBD\"],\n[2, 4,\"ANDA\"],\n[2, 4,\"BITA\"],\n[2, 4,\"LDA\"],\n[1, 0,\"???\"],\n[2, 4,\"EORA\"],\n[2, 4,\"ADCA\"],\n[2, 4,\"ORA\"],\n[2, 4,\"ADDA\"],\n[3, 8,\"CMPX\"],\n[2, 5,\"BSR\"],\n[3, 8,\"LDX\"],\n[1, 0,\"???\"],\n[2, 1,\"SUBA\"],\n[2, 1,\"CMPA\"],\n[2, 1,\"SBCA\"],\n[2, 1,\"SUBd\"],\n[2, 1,\"ANDA\"],\n[2, 1,\"BITA\"],\n[2, 1,\"LDA\"],\n[2, 1,\"STA\"],\n[2, 1,\"EORA\"],\n[2, 1,\"ADCA\"],\n[2, 1,\"ORA\"],\n[2, 1,\"ADDA\"],\n[2, 1,\"CMPX\"],\n[2, 1,\"JSR\"],\n[2, 1,\"LDX\"],\n[2, 1,\"STX\"],\n[2, 6,\"SUBA\"],\n[2, 6,\"CMPA\"],\n[2, 6,\"SBCA\"],\n[2, 6,\"SUBD\"],\n[2, 6,\"ANDA\"],\n[2, 6,\"BITA\"],\n[2, 6,\"LDA\"],\n[2, 6,\"STA\"],\n[2, 6,\"EORA\"],\n[2, 6,\"ADCA\"],\n[2, 6,\"ORA\"],\n[2, 6,\"ADDA\"],\n[2, 6,\"CMPX\"],\n[2, 6,\"JSR\"],\n[2, 6,\"LDX\"],\n[2, 6,\"STX\"],\n[3, 7,\"SUBA\"],\n[3, 7,\"CMPA\"],\n[3, 7,\"SBCA\"],\n[3, 7,\"SUBD\"],\n[3, 7,\"ANDA\"],\n[3, 7,\"BITA\"],\n[3, 7,\"LDA\"],\n[3, 7,\"STA\"],\n[3, 7,\"EORA\"],\n[3, 7,\"ADCA\"],\n[3, 7,\"ORA\"],\n[3, 7,\"ADDA\"],\n[3, 7,\"CMPX\"],\n[3, 7,\"JSR\"],\n[3, 7,\"LDX\"],\n[3, 7,\"STX\"],\n[2, 4,\"SUBB\"],\n[2, 4,\"CMPB\"],\n[2, 4,\"SBCB\"],\n[3, 8,\"ADDD\"],\n[2, 4,\"ANDB\"],\n[2, 4,\"BITB\"],\n[2, 4,\"LDB\"],\n[1, 0,\"???\"],\n[2, 4,\"EORB\"],\n[2, 4,\"ADCB\"],\n[2, 4,\"ORB\"],\n[2, 4,\"ADDB\"],\n[3, 8,\"LDD\"],\n[1, 0,\"???\"],\n[3, 8,\"LDU\"],\n[1, 0,\"???\"],\n[2, 1,\"SUBB\"],\n[2, 1,\"CMPB\"],\n[2, 1,\"SBCB\"],\n[2, 1,\"ADDD\"],\n[2, 1,\"ANDB\"],\n[2, 1,\"BITB\"],\n[2, 1,\"LDB\"],\n[2, 1,\"STB\"],\n[2, 1,\"EORB\"],\n[2, 1,\"ADCB\"],\n[2, 1,\"ORB \"],\n[2, 1,\"ADDB\"],\n[2, 1,\"LDD \"],\n[2, 1,\"STD \"],\n[2, 1,\"LDU \"],\n[2, 1,\"STU \"],\n[2, 6,\"SUBB\"],\n[2, 6,\"CMPB\"],\n[2, 6,\"SBCB\"],\n[2, 6,\"ADDD\"],\n[2, 6,\"ANDB\"],\n[2, 6,\"BITB\"],\n[2, 6,\"LDB\"],\n[2, 6,\"STB\"],\n[2, 6,\"EORB\"],\n[2, 6,\"ADCB\"],\n[2, 6,\"ORB\"],\n[2, 6,\"ADDB\"],\n[2, 6,\"LDD\"],\n[2, 6,\"STD\"],\n[2, 6,\"LDU\"],\n[2, 6,\"STU\"],\n[3, 7,\"SUBB\"],\n[3, 7,\"CMPB\"],\n[3, 7,\"SBCB\"],\n[3, 7,\"ADDD\"],\n[3, 7,\"ANDB\"],\n[3, 7,\"BITB\"],\n[3, 7,\"LDB\"],\n[3, 7,\"STB\"],\n[3, 7,\"EORB\"],\n[3, 7,\"ADCB\"],\n[3, 7,\"ORB\"],\n[3, 7,\"ADDB\"],\n[3, 7,\"LDD\"],\n[3, 7,\"STD\"],\n[3, 7,\"LDU\"],\n[3, 7,\"STU\"]\n];\n\nvar ds11 = {\n0x3F: [2,2,\"SWI3\"],\n0x83: [4,8,\"CMPU\"],\n0x8C: [4,8,\"CMPS\"],\n0x93: [3,1,\"CMPU\"],\n0x9C: [3,1,\"CMPS\"],\n0xA3: [3,6,\"CMPU\"],\n0xAC: [3,6,\"CMPS\"],\n0xB3: [4,7,\"CMPU\"],\n0xBC: [4,7,\"CMPS\"]\n};\n\nvar ds10 = {\n0x21:[5,3,\"LBRN\"],\n0x22:[5,3,\"LBHI\"],\n0x23:[5,3,\"LBLS\"],\n0x24:[5,3,\"LBCC\"],\n0x25:[5,3,\"LBCS\"],\n0x26:[5,3,\"LBNE\"],\n0x27:[5,3,\"LBEQ\"],\n0x28:[5,3,\"LBVC\"],\n0x29:[5,3,\"LBVS\"],\n0x2a:[5,3,\"LBPL\"],\n0x2b:[5,3,\"LBMI\"],\n0x2c:[5,3,\"LBGE\"],\n0x2d:[5,3,\"LBLT\"],\n0x2e:[5,3,\"LBGT\"],\n0x2f:[5,3,\"LBLE\"],\n0x3F:[2,2,\"SWI2\"],\n0x83:[4,8,\"CMPD\"],\n0x8C:[4,8,\"CMPY\"],\n0x8E:[4,8,\"LDY\"],\n0x93:[3,1,\"CMPD\"],\n0x9C:[3,1,\"CMPY\"],\n0x9E:[3,1,\"LDY\"],\n0x9F:[3,1,\"STY\"],\n0xA3:[3,6,\"CMPD\"],\n0xAC:[3,6,\"CMPY\"],\n0xAE:[3,6,\"LDY\"],\n0xAF:[3,6,\"STY\"],\n0xB3:[4,7,\"CMPD\"],\n0xBC:[4,7,\"CMPY\"],\n0xBE:[4,7,\"LDY\"],\n0xBF:[4,7,\"STY\"],\n0xCE:[4,8,\"LDS\"],\n0xDE:[3,1,\"LDS\"],\n0xDF:[3,1,\"STS\"],\n0xEE:[3,6,\"LDS\"],\n0xEF:[3,6,\"STS\"],\n0xFE:[4,7,\"LDS\"],\n0xFF:[4,7,\"STS\"]\n};\n/*\nILLEGAL 0\nDIRECT 1\nINHERENT 2\nBRANCH_REL_16 3\nIMMEDIAT_8 4\nBRANCH_REL_8 5\nINDEXED 6\nEXTENDED 7\nIMMEDIAT_16 8\n*/\n\nvar disasm = function(i,a,b,c,d,pc) {\n var toHexN = function(n,d) {\n var s = n.toString(16);\n while (s.length <d) {s = '0'+s;}\n return s.toUpperCase();\n };\n\n var toHex2 = function(n) {return toHexN(n & 0xff,2);};\n var toHex4 = function(n) {return toHexN(n,4);};\n var rx,ro,j;\n var sx = ds[i];\n if (i===0x10) {\n sx = ds10[a];\n if (sx===undefined) {\n return [\"???\",2];\n }\n i=a;a=b;b=c;c=d;\n }\n if (i===0x11) {\n sx = ds11[a];\n if (sx===undefined) {\n return [\"???\",2];\n }\n i=a;a=b;b=c;c=d;\n }\n var bytes = sx[0] as number;\n var mode = sx[1] as number;\n var mnemo = sx[2];\n\n switch (mode) {\n case 0: //invalid\n break;\n case 1: //direct page\n mnemo+=\"\\t$\"+toHex2(a); break;\n case 2: // inherent\n break;\n case 3: //brel16\n mnemo+=\"\\t#$\"+toHex4((a*256+b)<32768 ? (a*256+b+pc):(a*256+b+pc-65536)); break;\n case 4: //imm8\n mnemo+=\"\\t#$\"+toHex2(a); break;\n case 5: //brel8\n mnemo+=\"\\t#$\"+toHex4((a)<128 ? (a+pc+2):(a+pc-254)); break;\n case 6: //indexed, postbyte etc.\n mnemo+='\\t';\n var pb = a;\n var ixr = [\"X\",\"Y\",\"U\",\"S\"][(pb & 0x60)>>5];\n if (!(pb & 0x80)) {\n //direct5\n var disp = pb & 0x1f;\n if (disp>15) disp = disp-32;\n mnemo+=disp+','+ixr;\n break;\n }\n var ind = pb & 0x10;\n var mod = pb & 0x0f;\n var ofs8 = (b>127)?(b-256):b;\n var ofs16 = ((b*256+c)>32767)?((b*256+c)-65536):(b*256+c);\n if (!ind) {\n switch (mod) {\n case 0: mnemo += \",\"+ixr+'+'; break;\n case 1: mnemo += \",\"+ixr+'++'; break;\n case 2: mnemo += \",-\"+ixr; break;\n case 3: mnemo += \",--\"+ixr; break;\n case 4: mnemo += \",\"+ixr; break;\n case 5: mnemo += \"B,\"+ixr; break;\n case 6: mnemo += \"A,\"+ixr; break;\n case 7: mnemo += \"???\"; break;\n case 8: mnemo += ofs8+\",\"+ixr; bytes++; break;\n case 9: mnemo += ofs16+\",\"+ixr; bytes+=2; break;\n case 10: mnemo += \"???\"; break;\n case 11: mnemo += \"D,\"+ixr; break;\n case 12: mnemo += ofs8+\",PC\"; bytes++; break;\n case 13: mnemo += ofs16+\",PC\"; bytes+=2; break;\n case 14: mnemo += \"???\"; break;\n case 15: mnemo += \"$\"+toHex4((b*256+c)); bytes+=2; break;\n }\n } else {\n switch (mod) {\n case 0: mnemo += \"???\"; break;\n case 1: mnemo += \"[,\"+ixr+'++]'; break;\n case 2: mnemo += \"???\"; break;\n case 3: mnemo += \"[,--\"+ixr+']'; break;\n case 4: mnemo += \"[,\"+ixr+']'; break;\n case 5: mnemo += \"[B,\"+ixr+']'; break;\n case 6: mnemo += \"[A,\"+ixr+']'; break;\n case 7: mnemo += \"???\"; break;\n case 8: mnemo += \"[\"+ofs8+\",\"+ixr+']'; bytes++; break;\n case 9: mnemo += \"[\"+ofs16+\",\"+ixr+']'; bytes+=2; break;\n case 10: mnemo += \"???\"; break;\n case 11: mnemo += \"[D,\"+ixr+']'; break;\n case 12: mnemo += \"[\"+ofs8+\",PC]\"; bytes++; break;\n case 13: mnemo += \"[\"+ofs16+\",PC]\"; bytes+=2; break;\n case 14: mnemo += \"???\"; break;\n case 15: mnemo += \"[$\"+toHex4((b*256+c))+']'; bytes+=2; break;\n }\n }\n\n break;\n case 7: //extended\n mnemo+=\"\\t$\"+toHex4(a*256+b); break;\n case 8: //imm16\n mnemo+=\"\\t#$\"+toHex4(a*256+b); break;\n\n case 10: //pshs, puls\n rx = ['PC','U','Y','X','DP','B','A','CC'];\n ro = [];\n for (j=0;j<8;j++) {\n if ((a & 1)!==0) {ro.push(rx[7-j]);}\n a>>=1;\n }\n mnemo += '\\t'+ro.join(',');\n break;\n case 11: //pshs, puls\n rx = ['PC','S','Y','X','DP','B','A','CC'];\n ro = [];\n for (j=0;j<8;j++) {\n if ((a & 1)!==0) {ro.push(rx[7-j]);}\n a>>=1;\n }\n mnemo += '\\t'+ro.join(',');\n break;\n case 20: //TFR etc\n rx = ['D','X','Y','U','S','PC','?','?','A','B','CC','DP','?','?','?','?'];\n mnemo += '\\t'+rx[a>>4]+','+rx[a&0x0f];\n break;\n }\n\n return {line:mnemo,nbytes:bytes};\n };\n\n\n//---------- Exports\n\nreturn {\n steps: function(Ts){\n //T=0;\n while (Ts>0){\n Ts-=step();\n }\n },\n runFrame: function(Tt){\n while (T<Tt){\n step();\n }\n },\n advanceInsn: function() {\n return step();\n },\n T:function(){return T;},\n getTstates:function(){return T;},\n setTstates:function(t){T=t;},\n reset: reset,\n init: function(bt,ba,tck){\n byteTo=bt;\n byteAt=ba;\n ticks=tck;\n reset();\n },\n getPC: function() { return PC; },\n getSP: function() { return rS; },\n saveState: function() {\n return {\n PC:PC,\n SP:rS,\n U:rU,\n A:rA,\n B:rB,\n X:rX,\n Y:rY,\n DP:DP,\n CC:CC,\n T:T\n };\n },\n loadState: function(s) {\n PC=s.PC;\n rS=s.SP;\n rU=s.U;\n rA=s.A;\n rB=s.B;\n rX=s.X;\n rY=s.Y;\n DP=s.DP;\n CC=s.CC;\n T=s.T;\n },\n firq: function() {\n if (CC & F_FIRQMASK) return;\n PUSHW(PC);\n CC &= ~F_ENTIRE;\n PUSHB(CC);\n CC |= F_IRQMASK | F_FIRQMASK;\n PC = ReadWord(vecFIRQ);\n T += 9;\n },\n interrupt: function() {\n if (CC & F_IRQMASK) return;\n PUSHW(PC);\n PUSHW(rU);\n PUSHW(rY);\n PUSHW(rX);\n PUSHB(DP);\n PUSHB(rB);\n PUSHB(rA);\n CC |= F_ENTIRE;\n PUSHB(CC);\n CC |= F_IRQMASK;\n PC = ReadWord(vecIRQ);\n T += 18;\n },\n nmi: function() {\n PUSHW(PC);\n PUSHW(rU);\n PUSHW(rY);\n PUSHW(rX);\n PUSHB(DP);\n PUSHB(rB);\n PUSHB(rA);\n CC |= F_ENTIRE;\n PUSHB(CC);\n CC |= F_IRQMASK | F_FIRQMASK;\n PC = ReadWord(vecNMI);\n T += 18;\n },\n set:function(reg,value) {\n switch (reg.toUpperCase()) {\n case \"PC\": PC=value;return;\n case \"A\": rA=value;return;\n case \"B\": rB=value;return;\n case \"X\": rX=value;return;\n case \"Y\": rY=value;return;\n case \"SP\": rS=value;return;\n case \"U\": rU=value;return;\n case \"FLAGS\": CC=value;return;\n }\n },\n flagsToString: function() {\n var f='',fx = \"EFHINZVC\";\n for (var i=0;i<8;i++) {\n var n = CC&(0x80>>i);\n if (n===0) {f+=fx[i].toLowerCase();} else {f+=fx[i];}\n }\n return f;\n },\n disasm: disasm,\n isStable: function() { return true; }\n};\n\n};\n", "\nimport { CPU, Bus, ClockBased, SavesState, Interruptable } from \"../devices\";\n\n// Copyright 2015 by Paulo Augusto Peccin. See license.txt distributed with this file.\n\nexport var _MOS6502 = function() {\n var self = this;\n\n this.powerOn = function() {\n this.reset();\n };\n\n this.powerOff = function() {\n };\n\n this.clockPulse = function() {\n if (!RDY) return; // TODO Should be ignored in the last cycle of the instruction\n T++;\n instruction[T]();\n };\n\n this.connectBus = function(aBus) {\n bus = aBus;\n };\n\n this.setRDY = function(boo) {\n RDY = boo;\n };\n\n this.isRDY = function() {\n return RDY;\n }\n\n this.reset = function() {\n I = 1;\n T = -1;\n instruction = [ fetchOpcodeAndDecodeInstruction ]; // Bootstrap instruction\n PC = bus.read(RESET_VECTOR) | (bus.read(RESET_VECTOR + 1) << 8);\n this.setRDY(true);\n };\n\n // Interfaces\n var bus : Bus;\n var RDY : boolean = false;\n\n // Registers\n var PC : number = 0;\n var SP : number = 0;\n var A : number = 0;\n var X : number = 0;\n var Y : number = 0;\n\n // Status Bits\n var N : number = 0;\n var V : number = 0;\n var D : number = 0;\n var I : number = 0;\n var Z : number = 0;\n var C : number = 0;\n\n // Internal decoding registers\n var T : number = -1;\n var opcode : number = -1;\n var instruction : (() => void)[];\n var data : number = 0;\n var AD : number = 0;\n var BA : number = 0;\n var BALCrossed : boolean = false;\n var IA : number = 0;\n var branchOffset : number = 0;\n var branchOffsetCrossAdjust : number = 0;\n\n // Vectors\n const NMI_VECTOR = 0xfffa;\n const RESET_VECTOR = 0xfffc;\n const IRQ_VECTOR = 0xfffe;\n\n // Index registers names\n const rX = 0;\n const rY = 1;\n\n // Status bits names\n const bN = 7;\n const bV = 6;\n // const bE = 5;\t// Not used\n // const bB = 4;\t// Not used\n // const bD = 3; // Not used\n // const bI = 2; // Not used\n const bZ = 1;\n const bC = 0;\n\n // Auxiliary variables\n // TODO\n //noinspection JSUnusedGlobalSymbols\n this.debug = false;\n //noinspection JSUnusedGlobalSymbols\n this.trace = false;\n\n\n // Internal operations\n\n var fetchOpcodeAndDecodeInstruction = function() {\n opcode = bus.read(PC);\n instruction = instructions[opcode];\n T = 0;\n\n // if (self.trace) self.breakpoint(\"TRACE\");\n // console.log(\"PC: \" + PC + \", op: \" + opcode + \": \" + opcodes[opcode]);\n\n PC++;\n };\n\n var fetchNextOpcode = fetchOpcodeAndDecodeInstruction;\n\n var fetchOpcodeAndDiscard = function() {\n bus.read(PC);\n };\n\n var fetchBranchOffset = function() {\n branchOffset = bus.read(PC);\n PC++;\n };\n\n var fetchADL = function() {\n AD = bus.read(PC);\n PC++;\n };\n\n var fetchADH = function() {\n AD |= bus.read(PC) << 8;\n PC++;\n };\n\n var fetchADLFromBA = function() {\n AD = bus.read(BA);\n };\n\n var fetchADHFromBA = function() {\n AD |= bus.read(BA) << 8;\n };\n\n var fetchBAL = function() {\n BA = bus.read(PC);\n PC++;\n };\n\n var fetchBAH = function() {\n BA |= bus.read(PC) << 8;\n PC++;\n };\n\n var fetchBALFromIA = function() {\n BA = bus.read(IA);\n };\n\n var fetchBAHFromIA = function() {\n BA |= bus.read(IA) << 8;\n };\n\n var addXtoBAL = function() {\n var low = (BA & 255) + X;\n BALCrossed = low > 255;\n BA = (BA & 0xff00) | (low & 255);\n };\n\n var addYtoBAL = function() {\n var low = (BA & 255) + Y;\n BALCrossed = low > 255;\n BA = (BA & 0xff00) | (low & 255);\n };\n\n var add1toBAL = function() {\n var low = (BA & 255) + 1;\n BALCrossed = low > 255;\n BA = (BA & 0xff00) | (low & 255);\n };\n\n var add1toBAHifBALCrossed = function() {\n if (BALCrossed)\n BA = (BA + 0x0100) & 0xffff;\n };\n\n var fetchIAL = function() {\n IA = bus.read(PC);\n PC++;\n };\n\n var fetchIAH = function() {\n IA |= bus.read(PC) << 8;\n PC++;\n };\n\n var add1toIAL = function() {\n var low = (IA & 255) + 1;\n IA = (IA & 0xff00) | (low & 255);\n };\n\n var fetchDataFromImmediate = function() {\n data = bus.read(PC);\n PC++;\n };\n\n var fetchDataFromAD = function() {\n data = bus.read(AD);\n };\n\n var fetchDataFromBA = function() {\n data = bus.read(BA);\n };\n\n var writeDataToAD = function() {\n bus.write(AD, data);\n };\n\n var writeDataToBA = function() {\n bus.write(BA, data);\n };\n\n var addBranchOffsetToPCL = function() {\n var oldLow = (PC & 0x00ff);\n var newLow = (oldLow + branchOffset) & 255;\n // Negative offset?\n if (branchOffset > 127)\n branchOffsetCrossAdjust = (newLow > oldLow) ? -0x0100 : 0;\n else\n branchOffsetCrossAdjust = (newLow < oldLow) ? 0x0100 : 0;\n PC = (PC & 0xff00) | newLow;\n };\n\n var adjustPCHForBranchOffsetCross = function() {\n PC = (PC + branchOffsetCrossAdjust) & 0xffff;\n };\n\n var setZ = function(val) {\n Z = (val === 0) ? 1 : 0;\n };\n\n var setN = function(val) {\n N = (val & 0x080) ? 1 : 0;\n };\n\n var setV = function(boo) {\n V = boo ? 1 : 0;\n };\n\n var setC = function(boo) {\n C = boo ? 1 : 0;\n };\n\n var popFromStack = function() {\n SP = (SP + 1) & 255;\n return bus.read(0x0100 + SP);\n };\n\n var peekFromStack = function() {\n return bus.read(0x0100 + SP);\n };\n\n var pushToStack = function(val) {\n bus.write(0x0100 + SP, val);\n SP = (SP - 1) & 255;\n };\n\n var getStatusBits = function() {\n return N << 7 | V << 6 | 0x30 // Always push with E (bit 5) and B (bit 4) ON\n | D << 3 | I << 2 | Z << 1 | C;\n };\n\n var setStatusBits = function(val) {\n N = val >>> 7; V = val >>> 6 & 1; // E and B flags actually do not exist as real flags, so ignore\n D = val >>> 3 & 1; I = val >>> 2 & 1; Z = val >>> 1 & 1; C = val & 1;\n };\n\n var illegalOpcode = function(op) {\n if (self.debug) self.breakpoint(\"Illegal Opcode: \" + op);\n };\n\n\n // Addressing routines\n\n var implied = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var immediateRead = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchDataFromImmediate,\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var zeroPageRead = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL, // ADH will be zero\n fetchDataFromAD,\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var absoluteRead = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL,\n fetchADH,\n fetchDataFromAD,\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var indirectXRead = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function() {\n addXtoBAL();\n fetchADLFromBA();\n },\n function() {\n add1toBAL();\n fetchADHFromBA();\n },\n fetchDataFromAD,\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var absoluteIndexedRead = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL,\n fetchBAH,\n function() {\n addIndex();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n function() {\n if (BALCrossed) {\n fetchDataFromBA();\n } else {\n operation();\n fetchNextOpcode();\n }\n },\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n };\n\n var zeroPageIndexedRead = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function() {\n addIndex();\n fetchDataFromBA();\n },\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n };\n\n var indirectYRead = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchIAL, // IAH will be zero\n fetchBALFromIA,\n function() {\n add1toIAL();\n fetchBAHFromIA();\n },\n function() {\n addYtoBAL();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n function() {\n if(BALCrossed) {\n fetchDataFromBA();\n } else {\n operation();\n fetchNextOpcode();\n }\n },\n function() {\n operation();\n fetchNextOpcode();\n }\n ];\n };\n\n var zeroPageWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL, // ADH will be zero\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var absoluteWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL,\n fetchADH,\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var indirectXWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function() {\n addXtoBAL();\n fetchADLFromBA();\n },\n function() {\n add1toBAL();\n fetchADHFromBA();\n },\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var absoluteIndexedWrite = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL,\n fetchBAH,\n function() {\n addIndex();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n function() {\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n };\n\n var zeroPageIndexedWrite = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function() {\n addIndex();\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n };\n\n var indirectYWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchIAL, // IAH will be zero\n fetchBALFromIA,\n function() {\n add1toIAL();\n fetchBAHFromIA();\n },\n function() {\n addYtoBAL();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n function() {\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n\n\n var zeroPageReadModifyWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL, // ADH will be zero\n fetchDataFromAD,\n writeDataToAD,\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var absoluteReadModifyWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL,\n fetchADH,\n fetchDataFromAD,\n writeDataToAD,\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var zeroPageIndexedReadModifyWrite = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function () {\n addIndex();\n fetchDataFromBA();\n },\n writeDataToBA,\n function () {\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n };\n\n var absoluteIndexedReadModifyWrite = function(index) {\n var addIndex = index === rX ? addXtoBAL : addYtoBAL;\n return function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL,\n fetchBAH,\n function () {\n addIndex();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n fetchDataFromBA,\n writeDataToBA,\n function () {\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n };\n\n var indirectXReadModifyWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBAL, // BAH will be zero\n fetchDataFromBA,\n function() {\n addXtoBAL();\n fetchADLFromBA();\n },\n function() {\n add1toBAL();\n fetchADHFromBA();\n },\n fetchDataFromAD,\n writeDataToAD,\n function() {\n operation();\n writeDataToAD();\n },\n fetchNextOpcode\n ];\n };\n\n var indirectYReadModifyWrite = function(operation) {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchIAL, // IAH will be zero\n fetchBALFromIA,\n function() {\n add1toIAL();\n fetchBAHFromIA();\n },\n function() {\n addYtoBAL();\n fetchDataFromBA();\n add1toBAHifBALCrossed();\n },\n fetchDataFromBA,\n writeDataToBA,\n function() {\n operation();\n writeDataToBA();\n },\n fetchNextOpcode\n ];\n };\n\n\n // Instructions ========================================================================================\n\n // Complete instruction set\n var opcodes = new Array(256);\n var instructions = new Array(256);\n\n opcodes[0x00] = \"BRK\"; instructions[0x00] = BRK();\n opcodes[0x01] = \"ORA\"; instructions[0x01] = ORA(indirectXRead);\n opcodes[0x02] = \"uKIL\"; instructions[0x02] = uKIL();\n opcodes[0x03] = \"uSLO\"; instructions[0x03] = uSLO(indirectXReadModifyWrite);\n opcodes[0x04] = \"uNOP\"; instructions[0x04] = uNOP(zeroPageRead);\n opcodes[0x05] = \"ORA\"; instructions[0x05] = ORA(zeroPageRead);\n opcodes[0x06] = \"ASL\"; instructions[0x06] = ASL(zeroPageReadModifyWrite);\n opcodes[0x07] = \"uSLO\"; instructions[0x07] = uSLO(zeroPageReadModifyWrite);\n opcodes[0x08] = \"PHP\"; instructions[0x08] = PHP();\n opcodes[0x09] = \"ORA\"; instructions[0x09] = ORA(immediateRead);\n opcodes[0x0a] = \"ASL\"; instructions[0x0a] = ASL_ACC();\n opcodes[0x0b] = \"uANC\"; instructions[0x0b] = uANC(immediateRead);\n opcodes[0x0c] = \"uNOP\"; instructions[0x0c] = uNOP(absoluteRead);\n opcodes[0x0d] = \"ORA\"; instructions[0x0d] = ORA(absoluteRead);\n opcodes[0x0e] = \"ASL\"; instructions[0x0e] = ASL(absoluteReadModifyWrite);\n opcodes[0x0f] = \"uSLO\"; instructions[0x0f] = uSLO(absoluteReadModifyWrite);\n opcodes[0x10] = \"BPL\"; instructions[0x10] = Bxx(bN, 0); // BPL\n opcodes[0x11] = \"ORA\"; instructions[0x11] = ORA(indirectYRead);\n opcodes[0x12] = \"uKIL\"; instructions[0x12] = uKIL();\n opcodes[0x13] = \"uSLO\"; instructions[0x13] = uSLO(indirectYReadModifyWrite);\n opcodes[0x14] = \"uNOP\"; instructions[0x14] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0x15] = \"ORA\"; instructions[0x15] = ORA(zeroPageIndexedRead(rX));\n opcodes[0x16] = \"ASL\"; instructions[0x16] = ASL(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x17] = \"uSLO\"; instructions[0x17] = uSLO(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x18] = \"CLC\"; instructions[0x18] = CLC();\n opcodes[0x19] = \"ORA\"; instructions[0x19] = ORA(absoluteIndexedRead(rY));\n opcodes[0x1a] = \"uNOP\"; instructions[0x1a] = uNOP(implied);\n opcodes[0x1b] = \"uSLO\"; instructions[0x1b] = uSLO(absoluteIndexedReadModifyWrite(rY));\n opcodes[0x1c] = \"uNOP\"; instructions[0x1c] = uNOP(absoluteIndexedRead(rX));\n opcodes[0x1d] = \"ORA\"; instructions[0x1d] = ORA(absoluteIndexedRead(rX));\n opcodes[0x1e] = \"ASL\"; instructions[0x1e] = ASL(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x1f] = \"uSLO\"; instructions[0x1f] = uSLO(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x20] = \"JSR\"; instructions[0x20] = JSR();\n opcodes[0x21] = \"AND\"; instructions[0x21] = AND(indirectXRead);\n opcodes[0x22] = \"uKIL\"; instructions[0x22] = uKIL();\n opcodes[0x23] = \"uRLA\"; instructions[0x23] = uRLA(indirectXReadModifyWrite);\n opcodes[0x24] = \"BIT\"; instructions[0x24] = BIT(zeroPageRead);\n opcodes[0x25] = \"AND\"; instructions[0x25] = AND(zeroPageRead);\n opcodes[0x26] = \"ROL\"; instructions[0x26] = ROL(zeroPageReadModifyWrite);\n opcodes[0x27] = \"uRLA\"; instructions[0x27] = uRLA(zeroPageReadModifyWrite);\n opcodes[0x28] = \"PLP\"; instructions[0x28] = PLP();\n opcodes[0x29] = \"AND\"; instructions[0x29] = AND(immediateRead);\n opcodes[0x2a] = \"ROL\"; instructions[0x2a] = ROL_ACC();\n opcodes[0x2b] = \"uANC\"; instructions[0x2b] = uANC(immediateRead);\n opcodes[0x2c] = \"BIT\"; instructions[0x2c] = BIT(absoluteRead);\n opcodes[0x2d] = \"AND\"; instructions[0x2d] = AND(absoluteRead);\n opcodes[0x2e] = \"ROL\"; instructions[0x2e] = ROL(absoluteReadModifyWrite);\n opcodes[0x2f] = \"uRLA\"; instructions[0x2f] = uRLA(absoluteReadModifyWrite);\n opcodes[0x30] = \"BMI\"; instructions[0x30] = Bxx(bN, 1); // BMI\n opcodes[0x31] = \"AND\"; instructions[0x31] = AND(indirectYRead);\n opcodes[0x32] = \"uKIL\"; instructions[0x32] = uKIL();\n opcodes[0x33] = \"uRLA\"; instructions[0x33] = uRLA(indirectYReadModifyWrite);\n opcodes[0x34] = \"uNOP\"; instructions[0x34] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0x35] = \"AND\"; instructions[0x35] = AND(zeroPageIndexedRead(rX));\n opcodes[0x36] = \"ROL\"; instructions[0x36] = ROL(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x37] = \"uRLA\"; instructions[0x37] = uRLA(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x38] = \"SEC\"; instructions[0x38] = SEC();\n opcodes[0x39] = \"AND\"; instructions[0x39] = AND(absoluteIndexedRead(rY));\n opcodes[0x3a] = \"uNOP\"; instructions[0x3a] = uNOP(implied);\n opcodes[0x3b] = \"uRLA\"; instructions[0x3b] = uRLA(absoluteIndexedReadModifyWrite(rY));\n opcodes[0x3c] = \"uNOP\"; instructions[0x3c] = uNOP(absoluteIndexedRead(rX));\n opcodes[0x3d] = \"AND\"; instructions[0x3d] = AND(absoluteIndexedRead(rX));\n opcodes[0x3e] = \"ROL\"; instructions[0x3e] = ROL(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x3f] = \"uRLA\"; instructions[0x3f] = uRLA(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x40] = \"RTI\"; instructions[0x40] = RTI();\n opcodes[0x41] = \"EOR\"; instructions[0x41] = EOR(indirectXRead);\n opcodes[0x42] = \"uKIL\"; instructions[0x42] = uKIL();\n opcodes[0x43] = \"uSRE\"; instructions[0x43] = uSRE(indirectXReadModifyWrite);\n opcodes[0x44] = \"uNOP\"; instructions[0x44] = uNOP(zeroPageRead);\n opcodes[0x45] = \"EOR\"; instructions[0x45] = EOR(zeroPageRead);\n opcodes[0x46] = \"LSR\"; instructions[0x46] = LSR(zeroPageReadModifyWrite);\n opcodes[0x47] = \"uSRE\"; instructions[0x47] = uSRE(zeroPageReadModifyWrite);\n opcodes[0x48] = \"PHA\"; instructions[0x48] = PHA();\n opcodes[0x49] = \"EOR\"; instructions[0x49] = EOR(immediateRead);\n opcodes[0x4a] = \"LSR\"; instructions[0x4a] = LSR_ACC();\n opcodes[0x4b] = \"uASR\"; instructions[0x4b] = uASR(immediateRead);\n opcodes[0x4c] = \"JMP\"; instructions[0x4c] = JMP_ABS();\n opcodes[0x4d] = \"EOR\"; instructions[0x4d] = EOR(absoluteRead);\n opcodes[0x4e] = \"LSR\"; instructions[0x4e] = LSR(absoluteReadModifyWrite);\n opcodes[0x4f] = \"uSRE\"; instructions[0x4f] = uSRE(absoluteReadModifyWrite);\n opcodes[0x50] = \"BVC\"; instructions[0x50] = Bxx(bV, 0); // BVC\n opcodes[0x51] = \"EOR\"; instructions[0x51] = EOR(indirectYRead);\n opcodes[0x52] = \"uKIL\"; instructions[0x52] = uKIL();\n opcodes[0x53] = \"uSRE\"; instructions[0x53] = uSRE(indirectYReadModifyWrite);\n opcodes[0x54] = \"uNOP\"; instructions[0x54] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0x55] = \"EOR\"; instructions[0x55] = EOR(zeroPageIndexedRead(rX));\n opcodes[0x56] = \"LSR\"; instructions[0x56] = LSR(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x57] = \"uSRE\"; instructions[0x57] = uSRE(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x58] = \"CLI\"; instructions[0x58] = CLI();\n opcodes[0x59] = \"EOR\"; instructions[0x59] = EOR(absoluteIndexedRead(rY));\n opcodes[0x5a] = \"uNOP\"; instructions[0x5a] = uNOP(implied);\n opcodes[0x5b] = \"uSRE\"; instructions[0x5b] = uSRE(absoluteIndexedReadModifyWrite(rY));\n opcodes[0x5c] = \"uNOP\"; instructions[0x5c] = uNOP(absoluteIndexedRead(rX));\n opcodes[0x5d] = \"EOR\"; instructions[0x5d] = EOR(absoluteIndexedRead(rX));\n opcodes[0x5e] = \"LSR\"; instructions[0x5e] = LSR(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x5f] = \"uSRE\"; instructions[0x5f] = uSRE(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x60] = \"RTS\"; instructions[0x60] = RTS();\n opcodes[0x61] = \"ADC\"; instructions[0x61] = ADC(indirectXRead);\n opcodes[0x62] = \"uKIL\"; instructions[0x62] = uKIL();\n opcodes[0x63] = \"uRRA\"; instructions[0x63] = uRRA(indirectXReadModifyWrite);\n opcodes[0x64] = \"uNOP\"; instructions[0x64] = uNOP(zeroPageRead);\n opcodes[0x65] = \"ADC\"; instructions[0x65] = ADC(zeroPageRead);\n opcodes[0x66] = \"ROR\"; instructions[0x66] = ROR(zeroPageReadModifyWrite);\n opcodes[0x67] = \"uRRA\"; instructions[0x67] = uRRA(zeroPageReadModifyWrite);\n opcodes[0x68] = \"PLA\"; instructions[0x68] = PLA();\n opcodes[0x69] = \"ADC\"; instructions[0x69] = ADC(immediateRead);\n opcodes[0x6a] = \"ROR\"; instructions[0x6a] = ROR_ACC();\n opcodes[0x6b] = \"uARR\"; instructions[0x6b] = uARR(immediateRead);\n opcodes[0x6c] = \"JMP\"; instructions[0x6c] = JMP_IND();\n opcodes[0x6d] = \"ADC\"; instructions[0x6d] = ADC(absoluteRead);\n opcodes[0x6e] = \"ROR\"; instructions[0x6e] = ROR(absoluteReadModifyWrite);\n opcodes[0x6f] = \"uRRA\"; instructions[0x6f] = uRRA(absoluteReadModifyWrite);\n opcodes[0x70] = \"BVS\"; instructions[0x70] = Bxx(bV, 1); // BVS\n opcodes[0x71] = \"ADC\"; instructions[0x71] = ADC(indirectYRead);\n opcodes[0x72] = \"uKIL\"; instructions[0x72] = uKIL();\n opcodes[0x73] = \"uRRA\"; instructions[0x73] = uRRA(indirectYReadModifyWrite);\n opcodes[0x74] = \"uNOP\"; instructions[0x74] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0x75] = \"ADC\"; instructions[0x75] = ADC(zeroPageIndexedRead(rX));\n opcodes[0x76] = \"ROR\"; instructions[0x76] = ROR(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x77] = \"uRRA\"; instructions[0x77] = uRRA(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0x78] = \"SEI\"; instructions[0x78] = SEI();\n opcodes[0x79] = \"ADC\"; instructions[0x79] = ADC(absoluteIndexedRead(rY));\n opcodes[0x7a] = \"uNOP\"; instructions[0x7a] = uNOP(implied);\n opcodes[0x7b] = \"uRRA\"; instructions[0x7b] = uRRA(absoluteIndexedReadModifyWrite(rY));\n opcodes[0x7c] = \"uNOP\"; instructions[0x7c] = uNOP(absoluteIndexedRead(rX));\n opcodes[0x7d] = \"ADC\"; instructions[0x7d] = ADC(absoluteIndexedRead(rX));\n opcodes[0x7e] = \"ROR\"; instructions[0x7e] = ROR(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x7f] = \"uRRA\"; instructions[0x7f] = uRRA(absoluteIndexedReadModifyWrite(rX));\n opcodes[0x80] = \"uNOP\"; instructions[0x80] = uNOP(immediateRead);\n opcodes[0x81] = \"STA\"; instructions[0x81] = STA(indirectXWrite);\n opcodes[0x82] = \"uNOP\"; instructions[0x82] = uNOP(immediateRead);\n opcodes[0x83] = \"uSAX\"; instructions[0x83] = uSAX(indirectXWrite);\n opcodes[0x84] = \"STY\"; instructions[0x84] = STY(zeroPageWrite);\n opcodes[0x85] = \"STA\"; instructions[0x85] = STA(zeroPageWrite);\n opcodes[0x86] = \"STX\"; instructions[0x86] = STX(zeroPageWrite);\n opcodes[0x87] = \"uSAX\"; instructions[0x87] = uSAX(zeroPageWrite);\n opcodes[0x88] = \"DEY\"; instructions[0x88] = DEY();\n opcodes[0x89] = \"uNOP\"; instructions[0x89] = uNOP(immediateRead);\n opcodes[0x8a] = \"TXA\"; instructions[0x8a] = TXA();\n opcodes[0x8b] = \"uANE\"; instructions[0x8b] = uANE(immediateRead);\n opcodes[0x8c] = \"STY\"; instructions[0x8c] = STY(absoluteWrite);\n opcodes[0x8d] = \"STA\"; instructions[0x8d] = STA(absoluteWrite);\n opcodes[0x8e] = \"STX\"; instructions[0x8e] = STX(absoluteWrite);\n opcodes[0x8f] = \"uSAX\"; instructions[0x8f] = uSAX(absoluteWrite);\n opcodes[0x90] = \"BCC\"; instructions[0x90] = Bxx(bC, 0); // BCC\n opcodes[0x91] = \"STA\"; instructions[0x91] = STA(indirectYWrite);\n opcodes[0x92] = \"uKIL\"; instructions[0x92] = uKIL();\n opcodes[0x93] = \"uSHA\"; instructions[0x93] = uSHA(indirectYWrite);\n opcodes[0x94] = \"STY\"; instructions[0x94] = STY(zeroPageIndexedWrite(rX));\n opcodes[0x95] = \"STA\"; instructions[0x95] = STA(zeroPageIndexedWrite(rX));\n opcodes[0x96] = \"STX\"; instructions[0x96] = STX(zeroPageIndexedWrite(rY));\n opcodes[0x97] = \"uSAX\"; instructions[0x97] = uSAX(zeroPageIndexedWrite(rY));\n opcodes[0x98] = \"TYA\"; instructions[0x98] = TYA();\n opcodes[0x99] = \"STA\"; instructions[0x99] = STA(absoluteIndexedWrite(rY));\n opcodes[0x9a] = \"TXS\"; instructions[0x9a] = TXS();\n opcodes[0x9b] = \"uSHS\"; instructions[0x9b] = uSHS(absoluteIndexedWrite(rY));\n opcodes[0x9c] = \"uSHY\"; instructions[0x9c] = uSHY(absoluteIndexedWrite(rX));\n opcodes[0x9d] = \"STA\"; instructions[0x9d] = STA(absoluteIndexedWrite(rX));\n opcodes[0x9e] = \"uSHX\"; instructions[0x9e] = uSHX(absoluteIndexedWrite(rY));\n opcodes[0x9f] = \"uSHA\"; instructions[0x9f] = uSHA(absoluteIndexedWrite(rY));\n opcodes[0xa0] = \"LDY\"; instructions[0xa0] = LDY(immediateRead);\n opcodes[0xa1] = \"LDA\"; instructions[0xa1] = LDA(indirectXRead);\n opcodes[0xa2] = \"LDX\"; instructions[0xa2] = LDX(immediateRead);\n opcodes[0xa3] = \"uLAX\"; instructions[0xa3] = uLAX(indirectXRead);\n opcodes[0xa4] = \"LDY\"; instructions[0xa4] = LDY(zeroPageRead);\n opcodes[0xa5] = \"LDA\"; instructions[0xa5] = LDA(zeroPageRead);\n opcodes[0xa6] = \"LDX\"; instructions[0xa6] = LDX(zeroPageRead);\n opcodes[0xa7] = \"uLAX\"; instructions[0xa7] = uLAX(zeroPageRead);\n opcodes[0xa8] = \"TAY\"; instructions[0xa8] = TAY();\n opcodes[0xa9] = \"LDA\"; instructions[0xa9] = LDA(immediateRead);\n opcodes[0xaa] = \"TAX\"; instructions[0xaa] = TAX();\n opcodes[0xab] = \"uLXA\"; instructions[0xab] = uLXA(immediateRead);\n opcodes[0xac] = \"LDY\"; instructions[0xac] = LDY(absoluteRead);\n opcodes[0xad] = \"LDA\"; instructions[0xad] = LDA(absoluteRead);\n opcodes[0xae] = \"LDX\"; instructions[0xae] = LDX(absoluteRead);\n opcodes[0xaf] = \"uLAX\"; instructions[0xaf] = uLAX(absoluteRead);\n opcodes[0xb0] = \"BCS\"; instructions[0xb0] = Bxx(bC, 1); // BCS\n opcodes[0xb1] = \"LDA\"; instructions[0xb1] = LDA(indirectYRead);\n opcodes[0xb2] = \"uKIL\"; instructions[0xb2] = uKIL();\n opcodes[0xb3] = \"uLAX\"; instructions[0xb3] = uLAX(indirectYRead);\n opcodes[0xb4] = \"LDY\"; instructions[0xb4] = LDY(zeroPageIndexedRead(rX));\n opcodes[0xb5] = \"LDA\"; instructions[0xb5] = LDA(zeroPageIndexedRead(rX));\n opcodes[0xb6] = \"LDX\"; instructions[0xb6] = LDX(zeroPageIndexedRead(rY));\n opcodes[0xb7] = \"uLAX\"; instructions[0xb7] = uLAX(zeroPageIndexedRead(rY));\n opcodes[0xb8] = \"CLV\"; instructions[0xb8] = CLV();\n opcodes[0xb9] = \"LDA\"; instructions[0xb9] = LDA(absoluteIndexedRead(rY));\n opcodes[0xba] = \"TSX\"; instructions[0xba] = TSX();\n opcodes[0xbb] = \"uLAS\"; instructions[0xbb] = uLAS(absoluteIndexedRead(rY));\n opcodes[0xbc] = \"LDY\"; instructions[0xbc] = LDY(absoluteIndexedRead(rX));\n opcodes[0xbd] = \"LDA\"; instructions[0xbd] = LDA(absoluteIndexedRead(rX));\n opcodes[0xbe] = \"LDX\"; instructions[0xbe] = LDX(absoluteIndexedRead(rY));\n opcodes[0xbf] = \"uLAX\"; instructions[0xbf] = uLAX(absoluteIndexedRead(rY));\n opcodes[0xc0] = \"CPY\"; instructions[0xc0] = CPY(immediateRead);\n opcodes[0xc1] = \"CMP\"; instructions[0xc1] = CMP(indirectXRead);\n opcodes[0xc2] = \"uNOP\"; instructions[0xc2] = uNOP(immediateRead);\n opcodes[0xc3] = \"uDCP\"; instructions[0xc3] = uDCP(indirectXReadModifyWrite);\n opcodes[0xc4] = \"CPY\"; instructions[0xc4] = CPY(zeroPageRead);\n opcodes[0xc5] = \"CMP\"; instructions[0xc5] = CMP(zeroPageRead);\n opcodes[0xc6] = \"DEC\"; instructions[0xc6] = DEC(zeroPageReadModifyWrite);\n opcodes[0xc7] = \"uDCP\"; instructions[0xc7] = uDCP(zeroPageReadModifyWrite);\n opcodes[0xc8] = \"INY\"; instructions[0xc8] = INY();\n opcodes[0xc9] = \"CMP\"; instructions[0xc9] = CMP(immediateRead);\n opcodes[0xca] = \"DEX\"; instructions[0xca] = DEX();\n opcodes[0xcb] = \"uSBX\"; instructions[0xcb] = uSBX(immediateRead);\n opcodes[0xcc] = \"CPY\"; instructions[0xcc] = CPY(absoluteRead);\n opcodes[0xcd] = \"CMP\"; instructions[0xcd] = CMP(absoluteRead);\n opcodes[0xce] = \"DEC\"; instructions[0xce] = DEC(absoluteReadModifyWrite);\n opcodes[0xcf] = \"uDCP\"; instructions[0xcf] = uDCP(absoluteReadModifyWrite);\n opcodes[0xd0] = \"BNE\"; instructions[0xd0] = Bxx(bZ, 0); // BNE\n opcodes[0xd1] = \"CMP\"; instructions[0xd1] = CMP(indirectYRead);\n opcodes[0xd2] = \"uKIL\"; instructions[0xd2] = uKIL();\n opcodes[0xd3] = \"uDCP\"; instructions[0xd3] = uDCP(indirectYReadModifyWrite);\n opcodes[0xd4] = \"uNOP\"; instructions[0xd4] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0xd5] = \"CMP\"; instructions[0xd5] = CMP(zeroPageIndexedRead(rX));\n opcodes[0xd6] = \"DEC\"; instructions[0xd6] = DEC(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0xd7] = \"uDCP\"; instructions[0xd7] = uDCP(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0xd8] = \"CLD\"; instructions[0xd8] = CLD();\n opcodes[0xd9] = \"CMP\"; instructions[0xd9] = CMP(absoluteIndexedRead(rY));\n opcodes[0xda] = \"uNOP\"; instructions[0xda] = uNOP(implied);\n opcodes[0xdb] = \"uDCP\"; instructions[0xdb] = uDCP(absoluteIndexedReadModifyWrite(rY));\n opcodes[0xdc] = \"uNOP\"; instructions[0xdc] = uNOP(absoluteIndexedRead(rX));\n opcodes[0xdd] = \"CMP\"; instructions[0xdd] = CMP(absoluteIndexedRead(rX));\n opcodes[0xde] = \"DEC\"; instructions[0xde] = DEC(absoluteIndexedReadModifyWrite(rX));\n opcodes[0xdf] = \"uDCP\"; instructions[0xdf] = uDCP(absoluteIndexedReadModifyWrite(rX));\n opcodes[0xe0] = \"CPX\"; instructions[0xe0] = CPX(immediateRead);\n opcodes[0xe1] = \"SBC\"; instructions[0xe1] = SBC(indirectXRead);\n opcodes[0xe2] = \"uNOP\"; instructions[0xe2] = uNOP(immediateRead);\n opcodes[0xe3] = \"uISB\"; instructions[0xe3] = uISB(indirectXReadModifyWrite);\n opcodes[0xe4] = \"CPX\"; instructions[0xe4] = CPX(zeroPageRead);\n opcodes[0xe5] = \"SBC\"; instructions[0xe5] = SBC(zeroPageRead);\n opcodes[0xe6] = \"INC\"; instructions[0xe6] = INC(zeroPageReadModifyWrite);\n opcodes[0xe7] = \"uISB\"; instructions[0xe7] = uISB(zeroPageReadModifyWrite);\n opcodes[0xe8] = \"INX\"; instructions[0xe8] = INX();\n opcodes[0xe9] = \"SBC\"; instructions[0xe9] = SBC(immediateRead);\n opcodes[0xea] = \"NOP\"; instructions[0xea] = NOP();\n opcodes[0xeb] = \"SBC\"; instructions[0xeb] = SBC(immediateRead);\n opcodes[0xec] = \"CPX\"; instructions[0xec] = CPX(absoluteRead);\n opcodes[0xed] = \"SBC\"; instructions[0xed] = SBC(absoluteRead);\n opcodes[0xee] = \"INC\"; instructions[0xee] = INC(absoluteReadModifyWrite);\n opcodes[0xef] = \"uISB\"; instructions[0xef] = uISB(absoluteReadModifyWrite);\n opcodes[0xf0] = \"BEQ\"; instructions[0xf0] = Bxx(bZ, 1); // BEQ\n opcodes[0xf1] = \"SBC\"; instructions[0xf1] = SBC(indirectYRead);\n opcodes[0xf2] = \"uKIL\"; instructions[0xf2] = uKIL();\n opcodes[0xf3] = \"uISB\"; instructions[0xf3] = uISB(indirectYReadModifyWrite);\n opcodes[0xf4] = \"uNOP\"; instructions[0xf4] = uNOP(zeroPageIndexedRead(rX));\n opcodes[0xf5] = \"SBC\"; instructions[0xf5] = SBC(zeroPageIndexedRead(rX));\n opcodes[0xf6] = \"INC\"; instructions[0xf6] = INC(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0xf7] = \"uISB\"; instructions[0xf7] = uISB(zeroPageIndexedReadModifyWrite(rX));\n opcodes[0xf8] = \"SED\"; instructions[0xf8] = SED();\n opcodes[0xf9] = \"SBC\"; instructions[0xf9] = SBC(absoluteIndexedRead(rY));\n opcodes[0xfa] = \"uNOP\"; instructions[0xfa] = uNOP(implied);\n opcodes[0xfb] = \"uISB\"; instructions[0xfb] = uISB(absoluteIndexedReadModifyWrite(rY));\n opcodes[0xfc] = \"uNOP\"; instructions[0xfc] = uNOP(absoluteIndexedRead(rX));\n opcodes[0xfd] = \"SBC\"; instructions[0xfd] = SBC(absoluteIndexedRead(rX));\n opcodes[0xfe] = \"INC\"; instructions[0xfe] = INC(absoluteIndexedReadModifyWrite(rX));\n opcodes[0xff] = \"uISB\"; instructions[0xff] = uISB(absoluteIndexedReadModifyWrite(rX));\n\n\n // Single Byte instructions\n\n function ASL_ACC() {\n return implied(function() {\n setC(A > 127);\n A = (A << 1) & 255;\n setZ(A);\n setN(A);\n });\n }\n\n function CLC() {\n return implied(function() {\n C = 0;\n });\n }\n\n function CLD() {\n return implied(function() {\n D = 0;\n });\n }\n\n function CLI() {\n return implied(function() {\n I = 0;\n });\n }\n\n function CLV() {\n return implied(function() {\n V = 0;\n });\n }\n\n function DEX() {\n return implied(function() {\n X = (X - 1) & 255;\n setZ(X);\n setN(X);\n });\n }\n\n function DEY() {\n return implied(function() {\n Y = (Y - 1) & 255;\n setZ(Y);\n setN(Y);\n });\n }\n\n function INX() {\n return implied(function() {\n X = (X + 1) & 255;\n setZ(X);\n setN(X);\n });\n }\n\n function INY() {\n return implied(function() {\n Y = (Y + 1) & 255;\n setZ(Y);\n setN(Y);\n });\n }\n\n function LSR_ACC() {\n return implied(function() {\n C = A & 0x01;\n A >>>= 1;\n setZ(A);\n N = 0;\n });\n }\n\n function NOP() {\n return implied(function() {\n // nothing\n });\n }\n\n function ROL_ACC() {\n return implied(function() {\n var newC = A > 127;\n A = ((A << 1) | C) & 255;\n setC(newC);\n setZ(A);\n setN(A);\n });\n }\n\n function ROR_ACC() {\n return implied(function() {\n var newC = A & 0x01;\n A = (A >>> 1) | (C << 7);\n setC(newC);\n setZ(A);\n setN(A);\n });\n }\n\n function SEC() {\n return implied(function() {\n C = 1;\n });\n }\n\n function SED() {\n return implied(function() {\n D = 1;\n });\n }\n\n function SEI() {\n return implied(function() {\n I = 1;\n });\n }\n\n function TAX() {\n return implied(function() {\n X = A;\n setZ(X);\n setN(X);\n });\n }\n\n function TAY() {\n return implied(function() {\n Y = A;\n setZ(Y);\n setN(Y);\n });\n }\n\n function TSX() {\n return implied(function() {\n X = SP;\n setZ(X);\n setN(X);\n });\n }\n\n function TXA() {\n return implied(function() {\n A = X;\n setZ(A);\n setN(A);\n });\n }\n\n function TXS() {\n return implied(function() {\n SP = X;\n });\n }\n\n function TYA() {\n return implied(function() {\n A = Y;\n setZ(A);\n setN(A);\n });\n }\n\n function uKIL() {\n return [\n fetchOpcodeAndDecodeInstruction,\n function() {\n illegalOpcode(\"KIL/HLT/JAM\");\n },\n function() {\n T--; // Causes the processor to be stuck in this instruction forever\n }\n ];\n }\n\n function uNOP(addressing) {\n return addressing(function() {\n illegalOpcode(\"NOP/DOP\");\n // nothing\n });\n }\n\n\n // Internal Execution on Memory Data\n\n function ADC(addressing) {\n return addressing(function() {\n if (D) {\n var operand = data;\n var AL = (A & 15) + (operand & 15) + C;\n if (AL > 9) { AL += 6; }\n var AH = ((A >> 4) + (operand >> 4) + ((AL > 15)?1:0)) << 4;\n setZ((A + operand + C) & 255);\n setN(AH);\n setV(((A ^AH) & ~(A ^ operand)) & 128);\n if (AH > 0x9f) { AH += 0x60; }\n setC(AH > 255);\n A = (AH | (AL & 15)) & 255;\n } else {\n var add = A + data + C;\n setC(add > 255);\n setV(((A ^ add) & (data ^ add)) & 0x80);\n A = add & 255;\n setZ(A);\n setN(A);\n }\n });\n }\n\n function AND(addressing) {\n return addressing(function() {\n A &= data;\n setZ(A);\n setN(A);\n });\n }\n\n function BIT(addressing) {\n return addressing(function() {\n var par = data;\n setZ(A & par);\n setV(par & 0x40);\n setN(par);\n });\n }\n\n function CMP(addressing) {\n return addressing(function() {\n var val = (A - data) & 255;\n setC(A >= data);\n setZ(val);\n setN(val);\n });\n }\n\n function CPX(addressing) {\n return addressing(function() {\n var val = (X - data) & 255;\n setC(X >= data);\n setZ(val);\n setN(val);\n });\n }\n\n function CPY(addressing) {\n return addressing(function() {\n var val = (Y - data) & 255;\n setC(Y >= data);\n setZ(val);\n setN(val);\n });\n }\n\n function EOR(addressing) {\n return addressing(function() {\n A ^= data;\n setZ(A);\n setN(A);\n });\n }\n\n function LDA(addressing) {\n return addressing(function() {\n A = data;\n setZ(A);\n setN(A);\n });\n }\n\n function LDX(addressing) {\n return addressing(function() {\n X = data;\n setZ(X);\n setN(X);\n });\n }\n\n function LDY(addressing) {\n return addressing(function() {\n Y = data;\n setZ(Y);\n setN(Y);\n });\n }\n\n function ORA(addressing) {\n return addressing(function() {\n A |= data;\n setZ(A);\n setN(A);\n });\n }\n\n function SBC(addressing) {\n return addressing(function() {\n if (D) {\n var operand = data;\n var AL = (A & 15) - (operand & 15) - (1-C);\n var AH = (A >> 4) - (operand >> 4) - ((AL < 0)?1:0);\n if (AL < 0) { AL -= 6; }\n if (AH < 0) { AH -= 6; }\n var sub = A - operand - (1-C);\n setC(~sub & 256);\n setV(((A ^ operand) & (A ^ sub)) & 128);\n setZ(sub & 255);\n setN(sub);\n A = ((AH << 4) | (AL & 15)) & 255;\n } else {\n operand = (~data) & 255;\n sub = A + operand + C;\n setC(sub > 255);\n setV(((A ^ sub) & (operand ^ sub) & 0x80));\n A = sub & 255;\n setZ(A);\n setN(A);\n }\n });\n }\n\n function uANC(addressing) {\n return addressing(function() {\n illegalOpcode(\"ANC\");\n A &= data;\n setZ(A);\n N = C = (A & 0x080) ? 1 : 0;\n });\n }\n\n function uANE(addressing) {\n return addressing(function() {\n illegalOpcode(\"ANE\");\n // Exact operation unknown. Do nothing\n });\n }\n\n function uARR(addressing) {\n // Some sources say flags are affected per ROR, others say its more complex. The complex one is chosen\n return addressing(function() {\n illegalOpcode(\"ARR\");\n var val = A & data;\n var oldC = C ? 0x80 : 0;\n val = (val >>> 1) | oldC;\n A = val;\n setZ(val);\n setN(val);\n var comp = A & 0x60;\n if (comp == 0x60) \t\t{ C = 1; V = 0; }\n else if (comp == 0x00) \t{ C = 0; V = 0; }\n else if (comp == 0x20) \t{ C = 0; V = 1; }\n else if (comp == 0x40) \t{ C = 1; V = 1; }\n });\n }\n\n function uASR(addressing) {\n return addressing(function() {\n illegalOpcode(\"ASR\");\n var val = A & data;\n C = (val & 0x01);\t\t// bit 0\n val = val >>> 1;\n A = val;\n setZ(val);\n N = 0;\n });\n }\n\n function uLAS(addressing) {\n return addressing(function() {\n illegalOpcode(\"LAS\");\n var val = SP & data;\n A = val;\n X = val;\n SP = val;\n setZ(val);\n setN(val);\n });\n }\n\n function uLAX(addressing) {\n return addressing(function() {\n illegalOpcode(\"LAX\");\n var val = data;\n A = val;\n X = val;\n setZ(val);\n setN(val);\n });\n }\n\n function uLXA(addressing) {\n return addressing(function() {\n // Some sources say its an OR with $EE then AND with IMM, others exclude the OR,\n // others exclude both the OR and the AND. Excluding just the OR...\n illegalOpcode(\"LXA\");\n var val = A /* | 0xEE) */ & data;\n A = val;\n X = val;\n setZ(val);\n setN(val);\n });\n }\n\n function uSBX(addressing) {\n return addressing(function() {\n illegalOpcode(\"SBX\");\n var par = A & X;\n var val = data;\n var newX = (par - val) & 255;\n X = newX;\n setC(par >= val);\n setZ(newX);\n setN(newX);\n });\n }\n\n\n // Store operations\n\n function STA(addressing) {\n return addressing(function() {\n data = A;\n });\n }\n\n function STX(addressing) {\n return addressing(function() {\n data = X;\n });\n }\n\n function STY(addressing) {\n return addressing(function() {\n data = Y;\n });\n }\n\n function uSAX(addressing) {\n return addressing(function() {\n // Some sources say it would affect N and Z flags, some say it wouldn't. Chose not to affect\n illegalOpcode(\"SAX\");\n data = A & X;\n });\n }\n\n function uSHA(addressing) {\n return addressing(function() {\n illegalOpcode(\"SHA\");\n data = A & X & ((BA >>> 8) + 1) & 255; // A & X & (High byte of effective address + 1) !!!\n // data would also be stored BAH if page boundary is crossed. Unobservable, not needed here\n });\n }\n\n function uSHS(addressing) {\n return addressing(function() {\n illegalOpcode(\"SHS\");\n var val = A & X;\n SP = val;\n data = val & ((BA >>> 8) + 1) & 255; // A & X & (High byte of effective address + 1) !!!\n // data would also be stored BAH if page boundary is crossed. Unobservable, not needed here\n });\n }\n\n function uSHX(addressing) {\n return addressing(function() {\n illegalOpcode(\"SHX\");\n data = X & ((BA >>> 8) + 1) & 255; // X & (High byte of effective address + 1) !!!\n // data would also be stored BAH if page boundary is crossed. Unobservable, not needed here\n });\n }\n\n function uSHY(addressing) {\n return addressing(function() {\n illegalOpcode(\"SHY\");\n data = Y & ((BA >>> 8) + 1) & 255; // Y & (High byte of effective address + 1) !!!\n // data would also be stored BAH if page boundary is crossed. Unobservable, not needed here\n });\n }\n\n\n // Read-Modify-Write operations\n\n function ASL(addressing) {\n return addressing(function() {\n setC(data > 127);\n var par = (data << 1) & 255;\n data = par;\n setZ(par);\n setN(par);\n });\n }\n\n function DEC(addressing) {\n return addressing(function() {\n var par = (data - 1) & 255;\n data = par;\n setZ(par);\n setN(par);\n });\n }\n\n function INC(addressing) {\n return addressing(function() {\n var par = (data + 1) & 255;\n data = par;\n setZ(par);\n setN(par);\n });\n }\n\n function LSR(addressing) {\n return addressing(function() {\n C = data & 0x01;\n data >>>= 1;\n setZ(data);\n N = 0;\n });\n }\n\n function ROL(addressing) {\n return addressing(function() {\n var newC = data > 127;\n var par = ((data << 1) | C) & 255;\n data = par;\n setC(newC);\n setZ(par);\n setN(par);\n });\n }\n\n function ROR(addressing) {\n return addressing(function() {\n var newC = data & 0x01;\n var par = (data >>> 1) | (C << 7);\n data = par;\n setC(newC);\n setZ(par);\n setN(par);\n });\n }\n\n function uDCP(addressing) {\n return addressing(function() {\n illegalOpcode(\"DCP\");\n var par = (data - 1) & 255;\n data = par;\n par = A - par;\n setC(par >= 0);\n setZ(par);\n setN(par);\n });\n }\n\n function uISB(addressing) {\n return addressing(function() {\n illegalOpcode(\"ISB\");\n data = (data + 1) & 255; // ISB is the same as SBC but incs the operand first\n if (D) {\n var operand = data;\n var AL = (A & 15) - (operand & 15) - (1-C);\n var AH = (A >> 4) - (operand >> 4) - ((AL < 0)?1:0);\n if (AL < 0) { AL -= 6; }\n if (AH < 0) { AH -= 6; }\n var sub = A - operand - (1-C);\n setC(~sub & 256);\n setV(((A ^ operand) & (A ^ sub)) & 128);\n setZ(sub & 255);\n setN(sub);\n A = ((AH << 4) | (AL & 15)) & 255;\n } else {\n operand = (~data) & 255;\n sub = A + operand + C;\n setC(sub > 255);\n setV(((A ^ sub) & (operand ^ sub) & 0x80));\n A = sub & 255;\n setZ(A);\n setN(A);\n }\n });\n }\n\n function uRLA(addressing) {\n return addressing(function() {\n illegalOpcode(\"RLA\");\n var val = data;\n var oldC = C;\n setC(val & 0x80);\t\t// bit 7 was set\n val = ((val << 1) | oldC) & 255;\n data = val;\n A &= val;\n setZ(val); // TODO Verify. May be A instead of val in the flags setting\n setN(val);\n });\n }\n\n function uRRA(addressing) {\n return addressing(function() {\n illegalOpcode(\"RRA\");\n var val = data;\n var oldC = C ? 0x80 : 0;\n setC(val & 0x01);\t\t// bit 0 was set\n val = (val >>> 1) | oldC;\n data = val;\n // RRA is the same as ADC from here\n if (D) {\n var operand = data;\n var AL = (A & 15) + (operand & 15) + C;\n if (AL > 9) { AL += 6; }\n var AH = ((A >> 4) + (operand >> 4) + ((AL > 15)?1:0)) << 4;\n setZ((A + operand + C) & 255);\n setN(AH);\n setV(((A ^AH) & ~(A ^ operand)) & 128);\n if (AH > 0x9f) { AH += 0x60; }\n setC(AH > 255);\n A = (AH | (AL & 15)) & 255;\n } else {\n var add = A + data + C;\n setC(add > 255);\n setV(((A ^ add) & (data ^ add)) & 0x80);\n A = add & 255;\n setZ(A);\n setN(A);\n }\n });\n }\n\n function uSLO(addressing) {\n return addressing(function() {\n illegalOpcode(\"SLO\");\n var val = data;\n setC(val & 0x80);\t\t// bit 7 was set\n val = (val << 1) & 255;\n data = val;\n val = A | val;\n A = val;\n setZ(val);\n setN(val);\n });\n }\n\n function uSRE(addressing) {\n return addressing(function() {\n illegalOpcode(\"SRE\");\n var val = data;\n setC(val & 0x01);\t\t// bit 0 was set\n val = val >>> 1;\n data = val;\n val = (A ^ val) & 255;\n A = val;\n setZ(val);\n setN(val);\n });\n }\n\n\n // Miscellaneous operations\n\n function PHA() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n function() { pushToStack(A); },\n fetchNextOpcode\n ];\n }\n\n function PHP() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n function() { pushToStack(getStatusBits()); },\n fetchNextOpcode\n ];\n }\n\n function PLA() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n peekFromStack,\n function() {\n A = popFromStack();\n setZ(A);\n setN(A);\n },\n fetchNextOpcode\n ];\n }\n\n function PLP() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n peekFromStack,\n function() { setStatusBits(popFromStack()); },\n fetchNextOpcode\n ];\n }\n\n function JSR() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL,\n peekFromStack,\n function() { pushToStack((PC >>> 8) & 0xff); },\n function() { pushToStack(PC & 0xff); },\n fetchADH,\n function() { PC = AD; fetchNextOpcode(); }\n ];\n }\n\n function BRK() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchDataFromImmediate, // For debugging purposes, use operand as an arg for BRK!\n function() {\n if (self.debug) self.breakpoint(\"BRK \" + data);\n pushToStack((PC >>> 8) & 0xff);\n },\n function() { pushToStack(PC & 0xff); },\n function() { pushToStack(getStatusBits()); }, // set B flag\n function() { AD = bus.read(IRQ_VECTOR); },\n function() { AD |= bus.read(IRQ_VECTOR + 1) << 8; },\n function() { PC = AD; I = 1; fetchNextOpcode(); }\n ];\n }\n\n function IRQ() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchDataFromImmediate, // For debugging purposes, use operand as an arg for BRK!\n function() {\n if (self.debug) self.breakpoint(\"IRQ \" + data);\n pushToStack((PC >>> 8) & 0xff);\n },\n function() { pushToStack(PC & 0xff); },\n function() { pushToStack(getStatusBits() & ~0x10); }, // no BRK flag\n function() { AD = bus.read(IRQ_VECTOR); },\n function() { AD |= bus.read(IRQ_VECTOR + 1) << 8; },\n function() { PC = AD; fetchNextOpcode(); }\n ];\n }\n\n function NMI() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchDataFromImmediate,\n function() {\n if (self.debug) self.breakpoint(\"NMI \" + data);\n pushToStack((PC >>> 8) & 0xff);\n },\n function() { pushToStack(PC & 0xff); },\n function() { pushToStack(getStatusBits() & ~0x10); }, // no BRK flag\n function() { AD = bus.read(NMI_VECTOR); },\n function() { AD |= bus.read(NMI_VECTOR + 1) << 8; },\n function() { PC = AD; fetchNextOpcode(); }\n ];\n }\n\n function RTI() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n peekFromStack,\n function() { setStatusBits(popFromStack()); },\n function() { AD = popFromStack(); },\n function() { AD |= popFromStack() << 8; },\n function() { PC = AD; fetchNextOpcode(); }\n ];\n }\n\n function RTS() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchOpcodeAndDiscard,\n peekFromStack,\n function() { AD = popFromStack(); },\n function() { AD |= popFromStack() << 8; },\n function() { PC = AD; fetchDataFromImmediate(); },\n fetchNextOpcode\n ];\n }\n\n function JMP_ABS() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchADL,\n fetchADH,\n function() { PC = AD; fetchNextOpcode(); }\n ];\n }\n\n function JMP_IND() {\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchIAL, // IAH will be zero\n fetchIAH,\n fetchBALFromIA,\n function() {\n add1toIAL();\n fetchBAHFromIA();\n },\n function() { PC = BA; fetchNextOpcode(); }\n ];\n }\n\n function Bxx(reg, cond) {\n var branchTaken;\n if (reg === bZ) branchTaken = function() { return Z === cond; };\n else if (reg === bN) branchTaken = function() { return N === cond; };\n else if (reg === bC) branchTaken = function() { return C === cond; };\n else branchTaken = function() { return V === cond; };\n return [\n fetchOpcodeAndDecodeInstruction,\n fetchBranchOffset,\n function() {\n if (branchTaken()) {\n fetchOpcodeAndDiscard();\n addBranchOffsetToPCL();\n } else {\n fetchNextOpcode();\n }\n },\n function() {\n if(branchOffsetCrossAdjust) {\n fetchOpcodeAndDiscard();\n adjustPCHForBranchOffsetCross();\n } else {\n fetchNextOpcode();\n }\n },\n fetchNextOpcode\n ];\n }\n\n\n // Savestate -------------------------------------------\n\n this.saveState = function():MOS6502State {\n return {\n PC: (PC-1) & 0xffff,\n A: A, X: X, Y: Y, SP: SP,\n N: N, V: V, D: D, I: I, Z: Z, C: C,\n T: T, o: opcode, R: RDY?1:0,\n d: data, AD: AD, BA: BA, BC: BALCrossed?1:0, IA: IA,\n bo: branchOffset, boa: branchOffsetCrossAdjust\n };\n };\n\n this.loadState = function(state:MOS6502State) {\n PC = (state.PC+1) & 0xffff;\n A = state.A; X = state.X; Y = state.Y; SP = state.SP;\n N = state.N; V = state.V; D = state.D; I = state.I; Z = state.Z; C = state.C;\n T = state.T; opcode = state.o; RDY = !!state.R;\n data = state.d; AD = state.AD; BA = state.BA; BALCrossed = !!state.BC; IA = state.IA;\n branchOffset = state.bo; branchOffsetCrossAdjust = state.boa;\n instruction = opcode < 0 ? [ fetchOpcodeAndDecodeInstruction ] : instructions[opcode];\n };\n\n\n // Accessory methods\n\n this.toString = function() {\n return \"CPU \" +\n \" PC: \" + PC.toString(16) + \" op: \" + opcode.toString() + \" T: \" + T + \" data: \" + data + \"\\n\" +\n \" A: \" + A.toString(16) + \" X: \" + X.toString(16) + \" Y: \" + Y.toString(16) + \" SP: \" + SP.toString(16) + \" \" +\n \"N\" + N + \" \" + \"V\" + V + \" \" + \"D\" + D + \" \" + \"I\" + I + \" \" + \"Z\" + Z + \" \" + \"C\" + C + \" \";\n };\n\n this.breakpoint = function(mes) {\n //jt.Util.log(mes);\n if (this.trace) {\n var text = \"CPU Breakpoint! \" + (mes ? \"(\" + mes + \")\" : \"\") + \"\\n\\n\" + this.toString();\n //jt.Util.message(text);\n }\n };\n\n var cycletime = [\n 7, 6, 0, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7,\n 6, 6, 0, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7,\n 6, 6, 0, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7,\n 6, 6, 0, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7,\n 0, 6, 0, 6, 3, 3, 3, 3, 2, 0, 2, 0, 4, 4, 4, 4,\n 2, 6, 0, 0, 4, 4, 4, 4, 2, 5, 2, 0, 0, 5, 0, 0,\n 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 0, 4, 4, 4, 4,\n 2, 5, 0, 5, 4, 4, 4, 4, 2, 4, 2, 0, 4, 4, 4, 4,\n 2, 6, 0, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 3, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7,\n 2, 6, 0, 8, 3, 3, 5, 5, 2, 2, 2, 0, 4, 4, 6, 6,\n 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7\n ];\n\n var extracycles = [\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1,\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1\n ];\n\n var insnlengths = [\n 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3,\n 3, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3,\n 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3,\n 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3,\n 0, 2, 0, 2, 2, 2, 2, 2, 1, 0, 1, 0, 3, 3, 3, 3,\n 2, 2, 0, 0, 2, 2, 2, 3, 1, 3, 1, 0, 0, 3, 0, 0,\n 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 0, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 1, 0, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 0, 3, 3, 3, 3,\n 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3\n ];\n\n var validinsns = [\n 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 0, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,\n 3, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,\n 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,\n 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,\n 0, 2, 0, 0, 2, 2, 2, 0, 1, 0, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 0, 3, 0, 0,\n 2, 2, 2, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,\n 2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,\n 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0\n ];\n\n this.getOpcodeMetadata = function(opcode, address) {\n // TODO: more intelligent maximum cycles\n //var i = instructions[opcode];\n return {\n opcode:opcode,\n mnenomic:opcodes[opcode],\n minCycles:cycletime[opcode],\n maxCycles:cycletime[opcode] + extracycles[opcode],\n insnlength:insnlengths[opcode]\n };\n }\n\n // only call when isPCStable() is true\n this.setNMI = function() {\n instruction = NMI();\n T = 1;\n PC = (PC-1) & 0xffff;\n }\n this.setIRQ = function() {\n if (!I) { // only if not disabled\n instruction = IRQ();\n T = 1;\n PC = (PC-1) & 0xffff;\n }\n }\n\n this.getSP = function() { return SP; }\n this.getPC = function() { return (PC-1) & 0xffff; }\n this.getT = function() { return T; }\n this.isHalted = function() { return opcodes[opcode] == \"uKIL\"; }\n \n this.isPCStable = function() {\n return T == 0;\n }\n};\n\nexport interface MOS6502State {\nPC : number;\nSP : number;\nA : number;\nX : number;\nY : number;\nN : number;\nV : number;\nD : number;\nI : number;\nZ : number;\nC : number;\nT : number;\no : number;\nR : number;\nd : number;\nAD : number;\nBA : number;\nBC : number;\nIA : number;\nbo : number;\nboa : number;\n}\n\nexport enum MOS6502Interrupts { None=0, NMI=1, IRQ=2 };\n\nexport class MOS6502 implements CPU, ClockBased, SavesState<MOS6502State>, Interruptable<MOS6502Interrupts> {\n\n cpu = new _MOS6502();\n interruptType : MOS6502Interrupts = MOS6502Interrupts.None;\n \n connectMemoryBus(bus:Bus) {\n this.cpu.connectBus(bus);\n }\n advanceClock() {\n if (this.interruptType && this.isStable()) {\n switch (this.interruptType) {\n case MOS6502Interrupts.NMI: this.cpu.setNMI(); break;\n case MOS6502Interrupts.IRQ: this.cpu.setIRQ(); break;\n }\n this.interruptType = 0;\n }\n this.cpu.clockPulse();\n }\n advanceInsn() {\n do {\n this.advanceClock();\n } while (!this.isStable());\n }\n reset() {\n this.cpu.reset();\n this.interruptType = 0;\n }\n interrupt(itype:number) {\n if (this.interruptType != MOS6502Interrupts.NMI) {\n this.interruptType = itype;\n }\n }\n NMI() {\n this.interrupt(MOS6502Interrupts.NMI);\n }\n IRQ() {\n this.interrupt(MOS6502Interrupts.IRQ);\n }\n getSP() {\n return this.cpu.getSP();\n }\n getPC() {\n return this.cpu.getPC();\n }\n isHalted() {\n return this.cpu.isHalted();\n }\n saveState() {\n var s = this.cpu.saveState();\n s.it = this.interruptType;\n return s;\n }\n loadState(s) {\n this.cpu.loadState(s);\n this.interruptType = s.it;\n }\n isStable() : boolean {\n return this.cpu.isPCStable();\n }\n // TODO: metadata\n // TODO: disassembler\n}\n", "\nimport { RasterVideo, dumpRAM, AnimationTimer, ControllerPoller } from \"./emu\";\nimport { hex, printFlags, invertMap, byteToASCII } from \"./util\";\nimport { CodeAnalyzer } from \"./analysis\";\nimport { Segment, FileData } from \"./workertypes\";\nimport { disassemble6502 } from \"./cpu/disasm6502\";\nimport { disassembleZ80 } from \"./cpu/disasmz80\";\nimport { Z80 } from \"./cpu/ZilogZ80\";\n\nimport { Bus, Resettable, FrameBased, VideoSource, SampledAudioSource, AcceptsROM, AcceptsBIOS, AcceptsKeyInput, SavesState, SavesInputState, HasCPU, HasSerialIO, SerialIOInterface, AcceptsJoyInput } from \"./devices\";\nimport { Probeable, RasterFrameBased, AcceptsPaddleInput } from \"./devices\";\nimport { SampledAudio } from \"./audio\";\nimport { ProbeRecorder } from \"./probe\";\nimport { BaseWASMMachine } from \"./wasmplatform\";\nimport { CPU6809 } from \"./cpu/6809\";\nimport { _MOS6502 } from \"./cpu/MOS6502\";\n\n///\n\nexport interface OpcodeMetadata {\n minCycles: number;\n maxCycles: number;\n insnlength: number;\n opcode: number;\n}\n\nexport interface CpuState {\n PC:number;\n EPC?:number; // effective PC (for bankswitching)\n o?:number;/*opcode*/\n SP?:number\n /*\n A:number, X:number, Y:number, SP:number, R:boolean,\n N,V,D,Z,C:boolean*/\n};\nexport interface EmuState {\n c?:CpuState,\t// CPU state\n b?:Uint8Array|number[], \t// RAM (TODO: not for vcs, support Uint8Array)\n ram?:Uint8Array,\n o?:{},\t\t\t\t// verilog\n};\nexport interface EmuControlsState {\n}\nexport type DisasmLine = {\n line:string,\n nbytes:number,\n isaddr:boolean\n};\n\nexport type SymbolMap = {[ident:string]:number};\nexport type AddrSymbolMap = {[address:number]:string};\n\nexport class DebugSymbols {\n symbolmap : SymbolMap;\t// symbol -> address\n addr2symbol : AddrSymbolMap;\t// address -> symbol\n debuginfo : {}; // extra platform-specific debug info\n\n constructor(symbolmap : SymbolMap, debuginfo : {}) {\n this.symbolmap = symbolmap;\n this.debuginfo = debuginfo;\n this.addr2symbol = invertMap(symbolmap);\n //// TODO: shouldn't be necc.\n if (!this.addr2symbol[0x0]) this.addr2symbol[0x0] = '$00'; // needed for ...\n this.addr2symbol[0x10000] = '__END__'; // ... dump memory to work\n }\n}\n\ntype MemoryMapType = \"main\" | \"vram\";\ntype MemoryMap = { [type:string] : Segment[] };\n\nexport function isDebuggable(arg:any): arg is Debuggable {\n return arg && typeof arg.getDebugCategories === 'function';\n}\n\nexport interface Debuggable {\n getDebugCategories?() : string[];\n getDebugInfo?(category:string, state:EmuState) : string;\n}\n\nexport interface Platform {\n start() : void | Promise<void>;\n reset() : void;\n isRunning() : boolean;\n getToolForFilename(s:string) : string;\n getDefaultExtension() : string;\n getPresets?() : Preset[];\n pause() : void;\n resume() : void;\n loadROM(title:string, rom:any); // TODO: Uint8Array\n loadBIOS?(title:string, rom:Uint8Array);\n getROMExtension?(rom:FileData) : string;\n\n loadState?(state : EmuState) : void;\n saveState?() : EmuState;\n loadControlsState?(state : EmuControlsState) : void;\n saveControlsState?() : EmuControlsState;\n\n inspect?(ident:string) : string;\n disassemble?(addr:number, readfn:(addr:number)=>number) : DisasmLine;\n readAddress?(addr:number) : number;\n readVRAMAddress?(addr:number) : number;\n \n setFrameRate?(fps:number) : void;\n getFrameRate?() : number;\n\n setupDebug?(callback : BreakpointCallback) : void;\n clearDebug?() : void;\n step?() : void;\n runToVsync?() : void;\n runToPC?(pc:number) : void;\n runUntilReturn?() : void;\n stepBack?() : void;\n runEval?(evalfunc : DebugEvalCondition) : void;\n runToFrameClock?(clock : number) : void;\n stepOver?() : void;\n restartAtPC?(pc:number) : boolean;\n\n getOpcodeMetadata?(opcode:number, offset:number) : OpcodeMetadata; //TODO\n getSP?() : number;\n getPC?() : number;\n getOriginPC?() : number;\n newCodeAnalyzer?() : CodeAnalyzer;\n \n getPlatformName?() : string;\n getMemoryMap?() : MemoryMap;\n\n setRecorder?(recorder : EmuRecorder) : void;\n advance?(novideo? : boolean) : number;\n advanceFrameClock?(trap:DebugCondition, step:number) : number;\n showHelp?() : string;\n resize?() : void;\n\n getRasterScanline?() : number;\n getRasterLineClock?() : number;\n setBreakpoint?(id : string, cond : DebugCondition);\n clearBreakpoint?(id : string);\n hasBreakpoint?(id : string) : boolean;\n getCPUState?() : CpuState;\n\n debugSymbols? : DebugSymbols;\n getDebugTree?() : {};\n \n startProbing?() : ProbeRecorder;\n stopProbing?() : void;\n\n isBlocked?() : boolean; // is blocked, halted, or waiting for input?\n\n readFile?(path: string) : FileData;\n writeFile?(path: string, data: FileData) : boolean;\n sourceFileFetch?: (path:string) => FileData;\n\n getDownloadFile?() : {extension:string, blob:Blob};\n getDebugSymbolFile?() : {extension:string, blob:Blob};\n}\n\nexport interface Preset {\n id : string;\n name : string;\n chapter? : number;\n title? : string;\n}\n\nexport interface MemoryBus {\n read : (address:number) => number;\n write : (address:number, value:number) => void;\n contend?: (address:number, cycles:number) => number;\n isContended?: (address:number) => boolean;\n}\n\nexport type DebugCondition = () => boolean;\nexport type DebugEvalCondition = (c:CpuState) => boolean;\nexport type BreakpointCallback = (s:EmuState, msg?:string) => void;\n// for composite breakpoints w/ single debug function\nexport class BreakpointList {\n id2bp : {[id:string] : Breakpoint} = {};\n getDebugCondition() : DebugCondition {\n if (Object.keys(this.id2bp).length == 0) {\n return null; // no breakpoints\n } else {\n // evaluate all breakpoints\n return () => {\n var result = false;\n for (var id in this.id2bp)\n if (this.id2bp[id].cond())\n result = true;\n return result;\n };\n }\n }\n}\nexport interface Breakpoint {\n cond: DebugCondition;\n};\n\nexport interface EmuRecorder {\n frameRequested() : boolean;\n recordFrame(state : EmuState);\n}\n\n/////\n\nexport abstract class BasePlatform {\n recorder : EmuRecorder = null;\n debugSymbols : DebugSymbols;\n internalFiles : {[path:string] : FileData} = {};\n\n abstract loadState(state : EmuState) : void;\n abstract saveState() : EmuState;\n abstract pause() : void;\n abstract resume() : void;\n abstract advance(novideo? : boolean) : number;\n\n setRecorder(recorder : EmuRecorder) : void {\n this.recorder = recorder;\n }\n updateRecorder() {\n // are we recording and do we need to save a frame?\n if (this.recorder && (<Platform><any>this).isRunning() && this.recorder.frameRequested()) {\n this.recorder.recordFrame(this.saveState());\n }\n }\n inspect(sym: string) : string {\n return inspectSymbol((this as any) as Platform, sym);\n }\n getDebugTree() : {} {\n var o : any = { };\n o.state = this.saveState();\n if (this.debugSymbols?.debuginfo) o.debuginfo = this.debugSymbols.debuginfo;\n return o;\n }\n readFile(path: string) : FileData {\n return this.internalFiles[path];\n }\n writeFile(path: string, data: FileData) : boolean {\n this.internalFiles[path] = data;\n return true;\n }\n}\n\nexport abstract class BaseDebugPlatform extends BasePlatform {\n onBreakpointHit : BreakpointCallback;\n debugCallback : DebugCondition;\n debugSavedState : EmuState = null;\n debugBreakState : EmuState = null;\n debugTargetClock : number = 0;\n debugClock : number = 0;\n breakpoints : BreakpointList = new BreakpointList();\n frameCount : number = 0;\n\n abstract getCPUState() : CpuState;\n\n setBreakpoint(id : string, cond : DebugCondition) {\n if (cond) {\n this.breakpoints.id2bp[id] = {cond:cond};\n this.restartDebugging();\n } else {\n this.clearBreakpoint(id);\n }\n }\n clearBreakpoint(id : string) {\n delete this.breakpoints.id2bp[id];\n }\n hasBreakpoint(id : string) {\n return this.breakpoints.id2bp[id] != null;\n }\n getDebugCallback() : DebugCondition {\n return this.breakpoints.getDebugCondition();\n }\n setupDebug(callback : BreakpointCallback) : void {\n this.onBreakpointHit = callback;\n }\n clearDebug() {\n if (this.debugBreakState != null) {\n this.loadState(this.debugSavedState);\n }\n this.debugSavedState = null;\n this.debugBreakState = null;\n this.debugTargetClock = -1;\n this.debugClock = 0;\n this.onBreakpointHit = null;\n this.clearBreakpoint('debug');\n this.frameCount = 0;\n }\n setDebugCondition(debugCond : DebugCondition) {\n this.setBreakpoint('debug', debugCond);\n }\n resetDebugging() {\n if (this.debugSavedState) {\n this.loadState(this.debugSavedState);\n } else {\n this.debugSavedState = this.saveState();\n }\n this.debugClock = 0;\n this.debugCallback = this.getDebugCallback();\n this.debugBreakState = null;\n }\n restartDebugging() {\n this.resetDebugging();\n this.resume();\n }\n preFrame() {\n // save state before frame, to record any inputs that happened pre-frame\n if (this.debugCallback && !this.debugBreakState) {\n // save state every frame and rewind debug clocks\n this.debugSavedState = this.saveState();\n this.debugTargetClock -= this.debugClock;\n this.debugClock = 0;\n }\n }\n postFrame() {\n // reload debug state at end of frame after breakpoint\n if (this.debugCallback && this.debugBreakState) {\n this.loadState(this.debugBreakState);\n }\n this.frameCount++;\n }\n pollControls() {\n }\n nextFrame(novideo : boolean) : number {\n this.pollControls();\n this.updateRecorder();\n this.preFrame();\n var steps = this.advance(novideo);\n this.postFrame();\n return steps;\n }\n // default debugging\n abstract getSP() : number;\n abstract getPC() : number;\n abstract isStable() : boolean;\n\n evalDebugCondition() {\n if (this.debugCallback && !this.debugBreakState) {\n this.debugCallback();\n }\n }\n wasBreakpointHit() : boolean {\n return this.debugBreakState != null;\n }\n breakpointHit(targetClock : number, reason? : string) {\n console.log(this.debugTargetClock, targetClock, this.debugClock, this.isStable());\n this.debugTargetClock = targetClock;\n this.debugBreakState = this.saveState();\n console.log(\"Breakpoint at clk\", this.debugClock, \"PC\", this.debugBreakState.c.PC.toString(16));\n this.pause();\n if (this.onBreakpointHit) {\n this.onBreakpointHit(this.debugBreakState, reason);\n }\n }\n haltAndCatchFire(reason : string) {\n this.breakpointHit(this.debugClock, reason);\n }\n runEval(evalfunc : DebugEvalCondition) {\n this.setDebugCondition( () => {\n if (++this.debugClock >= this.debugTargetClock && this.isStable()) {\n var cpuState = this.getCPUState();\n if (evalfunc(cpuState)) {\n this.breakpointHit(this.debugClock);\n return true;\n } else {\n return false;\n }\n }\n });\n }\n runToPC(pc: number) {\n this.debugTargetClock++;\n this.runEval((c) => {\n return c.PC == pc;\n });\n }\n runUntilReturn() {\n var SP0 = this.getSP();\n this.runEval( (c:CpuState) : boolean => {\n return c.SP > SP0; // TODO: check for RTS/RET opcode\n });\n }\n runToFrameClock(clock : number) : void {\n this.restartDebugging();\n this.debugTargetClock = clock;\n this.runEval(() : boolean => { return true; });\n }\n step() {\n this.runToFrameClock(this.debugClock+1);\n }\n stepBack() {\n var prevState;\n var prevClock;\n var clock0 = this.debugTargetClock;\n this.restartDebugging();\n this.debugTargetClock = clock0 - 25; // TODO: depends on CPU\n this.runEval( (c:CpuState) : boolean => {\n if (this.debugClock < clock0) {\n prevState = this.saveState();\n prevClock = this.debugClock;\n return false;\n } else {\n if (prevState) {\n this.loadState(prevState);\n this.debugClock = prevClock;\n }\n return true;\n }\n });\n }\n runToVsync() {\n this.restartDebugging();\n var frame0 = this.frameCount;\n this.runEval( () : boolean => {\n return this.frameCount > frame0;\n });\n }\n}\n\nexport function inspectSymbol(platform : Platform, sym : string) : string {\n if (!platform.debugSymbols) return;\n var symmap = platform.debugSymbols.symbolmap;\n var addr2sym = platform.debugSymbols.addr2symbol;\n if (!symmap || !platform.readAddress) return null;\n var addr = symmap[\"_\"+sym] || symmap[sym]; // look for C or asm symbol\n if (!(typeof addr == 'number')) return null;\n var b = platform.readAddress(addr);\n // don't show 2 bytes if there's a symbol at the next address\n if (addr2sym && addr2sym[addr+1] != null) {\n return \"$\"+hex(addr,4) + \" = $\"+hex(b,2)+\" (\"+b+\" decimal)\"; // unsigned\n } else {\n let b2 = platform.readAddress(addr+1);\n let w = b | (b2<<8);\n return \"$\"+hex(addr,4) + \" = $\"+hex(b,2)+\" $\"+hex(b2,2)+\" (\"+((w<<16)>>16)+\" decimal)\"; // signed\n }\n}\n\n////// 6502\n\nexport function getToolForFilename_6502(fn:string) : string {\n if (fn.endsWith(\".pla\")) return \"plasm\";\n if (fn.endsWith(\".c\")) return \"cc65\";\n if (fn.endsWith(\".h\")) return \"cc65\";\n if (fn.endsWith(\".s\")) return \"ca65\";\n if (fn.endsWith(\".ca65\")) return \"ca65\";\n if (fn.endsWith(\".dasm\")) return \"dasm\";\n if (fn.endsWith(\".acme\")) return \"acme\";\n if (fn.endsWith(\".wiz\")) return \"wiz\";\n if (fn.endsWith(\".ecs\")) return \"ecs\";\n return \"dasm\"; // .a\n}\n\n// TODO: can merge w/ Z80?\nexport abstract class Base6502Platform extends BaseDebugPlatform {\n\n // some platforms store their PC one byte before or after the first opcode\n // so we correct when saving and loading from state\n debugPCDelta = -1;\n fixPC(c) { c.PC = (c.PC + this.debugPCDelta) & 0xffff; return c; }\n unfixPC(c) { c.PC = (c.PC - this.debugPCDelta) & 0xffff; return c;}\n getSP() { return this.getCPUState().SP };\n getPC() { return this.getCPUState().PC };\n isStable() { return !this.getCPUState()['T']; }\n abstract readAddress(addr:number) : number;\n\n newCPU(membus : MemoryBus) {\n var cpu = new _MOS6502();\n cpu.connectBus(membus);\n return cpu;\n }\n\n getOpcodeMetadata(opcode, offset) {\n return getOpcodeMetadata_6502(opcode, offset);\n }\n\n getOriginPC() : number {\n return (this.readAddress(0xfffc) | (this.readAddress(0xfffd) << 8)) & 0xffff;\n }\n\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n return disassemble6502(pc, read(pc), read(pc+1), read(pc+2));\n }\n getToolForFilename = getToolForFilename_6502;\n getDefaultExtension() { return \".a\"; };\n\n getDebugCategories() {\n return ['CPU','ZPRAM','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_6502(state.c);\n case 'ZPRAM': return dumpRAM(state.b||state.ram, 0x0, 0x100);\n case 'Stack': return dumpStackToString(<Platform><any>this, state.b||state.ram, 0x100, 0x1ff, 0x100+state.c.SP, 0x20);\n }\n }\n}\n\nexport function cpuStateToLongString_6502(c) : string {\n function decodeFlags(c) {\n var s = \"\";\n s += c.N ? \" N\" : \" -\";\n s += c.V ? \" V\" : \" -\";\n s += c.D ? \" D\" : \" -\";\n s += c.Z ? \" Z\" : \" -\";\n s += c.C ? \" C\" : \" -\";\n s += c.I ? \" I\" : \" -\";\n return s;\n }\n return \"PC \" + hex(c.PC,4) + \" \" + decodeFlags(c) + \"\\n\"\n + \" A \" + hex(c.A) + \" \" + (c.R ? \"\" : \"BUSY\") + \"\\n\"\n + \" X \" + hex(c.X) + \"\\n\"\n + \" Y \" + hex(c.Y) + \" \" + \"SP \" + hex(c.SP) + \"\\n\";\n}\n\nvar OPMETA_6502 = {\n cycletime: [\n 7, 6, 0, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7, 6, 6, 0, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7, 6, 6, 0, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7, 6, 6, 0, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7, 0, 6, 0, 6, 3, 3, 3, 3, 2, 0, 2, 0, 4, 4, 4, 4, 2, 6, 0, 0, 4, 4, 4, 4, 2, 5, 2, 0, 0, 5, 0, 0, 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 0, 4, 4, 4, 4, 2, 5, 0, 5, 4, 4, 4, 4, 2, 4, 2, 0, 4, 4, 4, 4, 2, 6, 0, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 3, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7, 2, 6, 0, 8, 3, 3, 5, 5, 2, 2, 2, 0, 4, 4, 6, 6, 2, 5, 0, 8, 4, 4, 6, 6, 2, 4, 0, 7, 4, 4, 7, 7\n ],\n extracycles: [\n 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1\n ],\n insnlengths: [\n 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3, 3, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3, 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3, 1, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3, 0, 2, 0, 2, 2, 2, 2, 2, 1, 0, 1, 0, 3, 3, 3, 3, 2, 2, 0, 0, 2, 2, 2, 3, 1, 3, 1, 0, 0, 3, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 0, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 1, 0, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 0, 3, 3, 3, 3, 2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 0, 3, 3, 3, 3, 3\n ],\n validinsns: [\n 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 0, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0, 3, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0, 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0, 1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0, 0, 2, 0, 0, 2, 2, 2, 0, 1, 0, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 0, 3, 0, 0, 2, 2, 2, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0, 2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0, 2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0\n ],\n}\n\nexport function getOpcodeMetadata_6502(opcode, address) {\n // TODO: more intelligent maximum cycles\n // TODO: must always be new object, b/c we might modify it\n return {\n opcode:opcode,\n minCycles:OPMETA_6502.cycletime[opcode],\n maxCycles:OPMETA_6502.cycletime[opcode] + OPMETA_6502.extracycles[opcode],\n insnlength:OPMETA_6502.insnlengths[opcode]\n };\n}\n\n////// Z80\n\nexport function cpuStateToLongString_Z80(c) {\n function decodeFlags(flags) {\n return printFlags(flags, [\"S\",\"Z\",,\"H\",,\"V\",\"N\",\"C\"], true);\n }\n return \"PC \" + hex(c.PC,4) + \" \" + decodeFlags(c.AF) + \" \" + (c.iff1?\"I\":\"-\") + (c.iff2?\"I\":\"-\") + \"\\n\"\n + \"SP \" + hex(c.SP,4) + \" IR \" + hex(c.IR,4) + \"\\n\"\n + \"IX \" + hex(c.IX,4) + \" IY \" + hex(c.IY,4) + \"\\n\"\n + \"AF \" + hex(c.AF,4) + \" BC \" + hex(c.BC,4) + \"\\n\"\n + \"DE \" + hex(c.DE,4) + \" HL \" + hex(c.HL,4) + \"\\n\"\n ;\n}\n\nexport abstract class BaseZ80Platform extends BaseDebugPlatform {\n\n _cpu;\n waitCycles : number = 0;\n\n newCPU(membus : MemoryBus, iobus : MemoryBus) {\n this._cpu = new Z80();\n this._cpu.connectMemoryBus(membus);\n this._cpu.connectIOBus(iobus);\n return this._cpu;\n }\n\n getPC() { return this._cpu.getPC(); }\n getSP() { return this._cpu.getSP(); }\n isStable() { return true; }\n\n // TODO: refactor other parts into here\n runCPU(cpu, cycles:number) : number {\n this._cpu = cpu; // TODO?\n this.waitCycles = 0; // TODO: needs to spill over betwenn calls\n if (this.wasBreakpointHit())\n return 0;\n var debugCond = this.getDebugCallback();\n var n = 0;\n this.waitCycles += cycles;\n while (this.waitCycles > 0) {\n if (debugCond && debugCond()) {\n debugCond = null;\n break;\n }\n var cyc = cpu.advanceInsn();\n n += cyc;\n this.waitCycles -= cyc;\n }\n return n;\n }\n\n getToolForFilename = getToolForFilename_z80;\n getDefaultExtension() { return \".c\"; };\n // TODO: Z80 opcode metadata\n //this.getOpcodeMetadata = function() { }\n\n getDebugCategories() {\n return ['CPU','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_Z80(state.c);\n case 'Stack': {\n var sp = (state.c.SP-1) & 0xffff;\n var start = sp & 0xff00;\n var end = start + 0xff;\n if (sp == 0) sp = 0x10000;\n console.log(sp,start,end);\n return dumpStackToString(<Platform><any>this, [], start, end, sp, 0xcd);\n }\n }\n }\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n return disassembleZ80(pc, read(pc), read(pc+1), read(pc+2), read(pc+3));\n }\n}\n\nexport function getToolForFilename_z80(fn:string) : string {\n if (fn.endsWith(\".c\")) return \"sdcc\";\n if (fn.endsWith(\".h\")) return \"sdcc\";\n if (fn.endsWith(\".s\")) return \"sdasz80\";\n if (fn.endsWith(\".ns\")) return \"naken\";\n if (fn.endsWith(\".scc\")) return \"sccz80\";\n if (fn.endsWith(\".z\")) return \"zmac\";\n if (fn.endsWith(\".wiz\")) return \"wiz\";\n return \"zmac\";\n}\n\n////// 6809\n\nexport function cpuStateToLongString_6809(c) {\n function decodeFlags(flags) {\n return printFlags(flags, [\"E\",\"F\",\"H\",\"I\", \"N\",\"Z\",\"V\",\"C\"], true);\n }\n return \"PC \" + hex(c.PC,4) + \" \" + decodeFlags(c.CC) + \"\\n\"\n + \"SP \" + hex(c.SP,4) + \"\\n\"\n + \"DP \" + hex(c.DP,2) + \"\\n\"\n + \" A \" + hex(c.A,2) + \"\\n\"\n + \" B \" + hex(c.B,2) + \"\\n\"\n + \" X \" + hex(c.X,4) + \"\\n\"\n + \" Y \" + hex(c.Y,4) + \"\\n\"\n + \" U \" + hex(c.U,4) + \"\\n\"\n ;\n}\n\nexport function getToolForFilename_6809(fn:string) : string {\n if (fn.endsWith(\".c\")) return \"cmoc\";\n if (fn.endsWith(\".h\")) return \"cmoc\";\n if (fn.endsWith(\".xasm\")) return \"xasm6809\";\n return \"lwasm\";\n}\n\nexport abstract class Base6809Platform extends BaseZ80Platform {\n\n newCPU(membus : MemoryBus) {\n var cpu = Object.create(CPU6809());\n cpu.init(membus.write, membus.read, 0);\n return cpu;\n }\n\n cpuStateToLongString(c:CpuState) {\n return cpuStateToLongString_6809(c);\n }\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n // TODO: don't create new CPU\n return Object.create(CPU6809()).disasm(read(pc), read(pc+1), read(pc+2), read(pc+3), read(pc+4), pc);\n }\n getDefaultExtension() : string { return \".asm\"; };\n //this.getOpcodeMetadata = function() { }\n getToolForFilename = getToolForFilename_6809;\n getDebugCategories() {\n return ['CPU','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_6809(state.c);\n default: return super.getDebugInfo(category, state);\n }\n }\n}\n\n\n//TODO: how to get stack_end?\nexport function dumpStackToString(platform:Platform, mem:Uint8Array|number[], start:number, end:number, sp:number, jsrop:number, bigendian?:boolean) : string {\n var s = \"\";\n var nraw = 0;\n //s = dumpRAM(mem.slice(start,start+end+1), start, end-start+1);\n function read(addr) {\n if (addr < mem.length) return mem[addr];\n else return platform.readAddress(addr);\n }\n while (sp < end) {\n sp++;\n // see if there's a JSR on the stack here\n // TODO: make work with roms and memory maps\n var addr = read(sp) + read(sp+1)*256;\n if (bigendian) { addr = ((addr & 0xff) << 8) | ((addr & 0xff00) >> 8) }\n var jsrofs = jsrop==0x20 ? -2 : -3; // 6502 vs Z80\n var opcode = read(addr + jsrofs); // might be out of bounds\n if (opcode == jsrop) { // JSR\n s += \"\\n$\" + hex(sp) + \": \";\n s += hex(addr,4) + \" \" + lookupSymbol(platform, addr, true);\n sp++;\n nraw = 0;\n } else {\n if (nraw == 0)\n s += \"\\n$\" + hex(sp) + \": \";\n s += hex(read(sp)) + \" \";\n if (++nraw == 8) nraw = 0;\n }\n }\n return s+\"\\n\";\n}\n\n// TODO: slow, funky, uses global\nexport function lookupSymbol(platform:Platform, addr:number, extra:boolean) {\n var start = addr;\n var addr2symbol = platform.debugSymbols && platform.debugSymbols.addr2symbol;\n while (addr2symbol && addr >= 0) {\n var sym = addr2symbol[addr];\n if (sym) { // return first symbol we find\n var sym = addr2symbol[addr];\n return extra ? (sym + \" + $\" + hex(start-addr)) : sym;\n }\n if (!extra) break;\n addr--;\n }\n return \"\";\n}\n\n/// new Machine platform adapters\n\nexport interface Machine extends Bus, Resettable, FrameBased, AcceptsROM, HasCPU, SavesState<EmuState>, SavesInputState<any> {\n}\n\nexport function hasVideo(arg:any): arg is VideoSource {\n return typeof arg.connectVideo === 'function';\n}\nexport function hasAudio(arg:any): arg is SampledAudioSource {\n return typeof arg.connectAudio === 'function';\n}\nexport function hasKeyInput(arg:any): arg is AcceptsKeyInput {\n return typeof arg.setKeyInput === 'function';\n}\nexport function hasJoyInput(arg:any): arg is AcceptsJoyInput {\n return typeof arg.setJoyInput === 'function';\n}\nexport function hasPaddleInput(arg:any): arg is AcceptsPaddleInput {\n return typeof arg.setPaddleInput === 'function';\n}\nexport function isRaster(arg:any): arg is RasterFrameBased {\n return typeof arg.getRasterY === 'function';\n}\nexport function hasProbe(arg:any): arg is Probeable {\n return typeof arg.connectProbe == 'function';\n}\nexport function hasBIOS(arg:any): arg is AcceptsBIOS {\n return typeof arg.loadBIOS == 'function';\n}\nexport function hasSerialIO(arg:any): arg is HasSerialIO {\n return typeof arg.connectSerialIO === 'function';\n}\n\nexport abstract class BaseMachinePlatform<T extends Machine> extends BaseDebugPlatform implements Platform {\n machine : T;\n mainElement : HTMLElement;\n timer : AnimationTimer;\n video : RasterVideo;\n audio : SampledAudio;\n poller : ControllerPoller;\n serialIOInterface : SerialIOInterface;\n serialVisualizer : SerialIOVisualizer;\n\n probeRecorder : ProbeRecorder;\n startProbing;\n stopProbing;\n\n abstract newMachine() : T;\n abstract getToolForFilename(s:string) : string;\n abstract getDefaultExtension() : string;\n abstract getPresets() : Preset[];\n \n constructor(mainElement : HTMLElement) {\n super();\n this.mainElement = mainElement;\n }\n\n reset() {\n this.machine.reset();\n if (this.serialVisualizer != null) this.serialVisualizer.reset();\n }\n loadState(s) { this.machine.loadState(s); }\n saveState() { return this.machine.saveState(); }\n getSP() { return this.machine.cpu.getSP(); }\n getPC() { return this.machine.cpu.getPC(); }\n isStable() \t { return this.machine.cpu.isStable(); }\n getCPUState() { return this.machine.cpu.saveState(); }\n loadControlsState(s) { this.machine.loadControlsState(s); }\n saveControlsState() { return this.machine.saveControlsState(); }\n \n async start() {\n this.machine = this.newMachine();\n const m = this.machine;\n // block on WASM loading\n if (m instanceof BaseWASMMachine) {\n await m.loadWASM();\n }\n var videoFrequency;\n if (hasVideo(m)) {\n var vp = m.getVideoParams();\n this.video = new RasterVideo(this.mainElement, vp.width, vp.height, \n {overscan: !!vp.overscan,\n rotate: vp.rotate|0,\n aspect: vp.aspect});\n this.video.create();\n m.connectVideo(this.video.getFrameData());\n // TODO: support keyboard w/o video?\n if (hasKeyInput(m)) {\n this.video.setKeyboardEvents(m.setKeyInput.bind(m));\n this.poller = new ControllerPoller(m.setKeyInput.bind(m));\n }\n videoFrequency = vp.videoFrequency;\n }\n this.timer = new AnimationTimer(videoFrequency || 60, this.nextFrame.bind(this));\n if (hasAudio(m)) {\n var ap = m.getAudioParams();\n this.audio = new SampledAudio(ap.sampleRate);\n this.audio.start();\n m.connectAudio(this.audio);\n }\n if (hasPaddleInput(m)) {\n this.video.setupMouseEvents();\n }\n if (hasProbe(m)) {\n this.probeRecorder = new ProbeRecorder(m);\n this.startProbing = () => {\n m.connectProbe(this.probeRecorder);\n return this.probeRecorder;\n };\n this.stopProbing = () => {\n m.connectProbe(null);\n };\n }\n if (hasBIOS(m)) {\n this.loadBIOS = (title, data) => {\n m.loadBIOS(data, title);\n };\n }\n if (hasSerialIO(m)) {\n if (this.serialIOInterface == null) {\n this.serialVisualizer = new SerialIOVisualizer(this.mainElement, m);\n } else {\n m.connectSerialIO(this.serialIOInterface);\n }\n }\n }\n \n loadROM(title, data) {\n this.machine.loadROM(data, title);\n this.reset();\n }\n\n loadBIOS : (title, data) => void; // only set if hasBIOS() is true\n\n pollControls() {\n this.poller && this.poller.poll();\n if (hasPaddleInput(this.machine)) {\n this.machine.setPaddleInput(0, this.video.paddle_x);\n this.machine.setPaddleInput(1, this.video.paddle_y);\n }\n // TODO: put into interface\n if (this.machine['pollControls']) {\n this.machine['pollControls']();\n }\n }\n\n advance(novideo:boolean) {\n let trap = this.getDebugCallback();\n var steps = this.machine.advanceFrame(trap);\n if (!novideo && this.video) this.video.updateFrame();\n if (!novideo && this.serialVisualizer) this.serialVisualizer.refresh();\n return steps;\n }\n\n advanceFrameClock(trap, step) {\n if (!(step > 0)) return;\n if (this.machine instanceof BaseWASMMachine) {\n return this.machine.advanceFrameClock(trap, step);\n } else {\n return this.machine.advanceFrame(() => {\n return --step <= 0;\n });\n }\n }\n\n isRunning() {\n return this.timer && this.timer.isRunning();\n }\n\n resume() {\n this.timer.start();\n this.audio && this.audio.start();\n }\n\n pause() {\n this.timer.stop();\n this.audio && this.audio.stop();\n }\n\n // so probe views stick around TODO: must be a better way?\n runToVsync() {\n this.restartDebugging();\n var flag = false;\n this.runEval( () : boolean => {\n if (this.getRasterScanline() > 0) flag = true;\n else return flag;\n });\n }\n\n // TODO: reset target clock counter\n getRasterScanline() {\n return isRaster(this.machine) && this.machine.getRasterY();\n }\n\n readAddress(addr : number) : number {\n return this.machine.read(addr);\n }\n\n getDebugCategories() {\n if (isDebuggable(this.machine))\n return this.machine.getDebugCategories();\n }\n getDebugInfo(category:string, state:EmuState) : string {\n return isDebuggable(this.machine) && this.machine.getDebugInfo(category, state);\n }\n}\n\n// TODO: move debug info into CPU?\n\nexport abstract class Base6502MachinePlatform<T extends Machine> extends BaseMachinePlatform<T> {\n\n getOpcodeMetadata = getOpcodeMetadata_6502;\n getToolForFilename = getToolForFilename_6502;\n\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n return disassemble6502(pc, read(pc), read(pc+1), read(pc+2));\n }\n getDebugCategories() {\n if (isDebuggable(this.machine))\n return this.machine.getDebugCategories();\n else\n return ['CPU','ZPRAM','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_6502(state.c);\n case 'ZPRAM': return dumpRAM(state.b||state.ram, 0x0, 0x100);\n case 'Stack': return dumpStackToString(<Platform><any>this, state.b||state.ram, 0x100, 0x1ff, 0x100+state.c.SP, 0x20);\n default: return isDebuggable(this.machine) && this.machine.getDebugInfo(category, state);\n }\n }\n}\n\nexport abstract class BaseZ80MachinePlatform<T extends Machine> extends BaseMachinePlatform<T> {\n\n //getOpcodeMetadata = getOpcodeMetadata_z80;\n getToolForFilename = getToolForFilename_z80;\n\n getDebugCategories() {\n if (isDebuggable(this.machine))\n return this.machine.getDebugCategories();\n else\n return ['CPU','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_Z80(state.c);\n case 'Stack': {\n var sp = (state.c.SP-1) & 0xffff;\n var start = sp & 0xff00;\n var end = start + 0xff;\n if (sp == 0) sp = 0x10000;\n return dumpStackToString(<Platform><any>this, [], start, end, sp, 0xcd);\n }\n default: return isDebuggable(this.machine) && this.machine.getDebugInfo(category, state);\n }\n }\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n return disassembleZ80(pc, read(pc), read(pc+1), read(pc+2), read(pc+3));\n }\n\n}\n\nexport abstract class Base6809MachinePlatform<T extends Machine> extends BaseMachinePlatform<T> {\n\n getToolForFilename = getToolForFilename_6809;\n\n getDebugCategories() {\n if (isDebuggable(this.machine))\n return this.machine.getDebugCategories();\n else\n return ['CPU','Stack'];\n }\n getDebugInfo(category:string, state:EmuState) : string {\n switch (category) {\n case 'CPU': return cpuStateToLongString_6809(state.c);\n case 'Stack': {\n var sp = (state.c.SP-1) & 0xffff;\n var start = sp & 0xff00;\n var end = start + 0xff;\n if (sp == 0) sp = 0x10000;\n return dumpStackToString(<Platform><any>this, [], start, end, sp, 0x17, true);\n }\n default: return super.getDebugInfo(category, state);\n }\n }\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n // TODO: don't create new CPU\n return Object.create(CPU6809()).disasm(read(pc), read(pc+1), read(pc+2), read(pc+3), read(pc+4), pc);\n }\n}\n\n///\n\nclass SerialIOVisualizer {\n\n textarea : HTMLTextAreaElement;\n //vlist: VirtualTextScroller;\n device: HasSerialIO;\n lastOutCount = -1;\n lastInCount = -1;\n\n constructor(parentElement: HTMLElement, device: HasSerialIO) {\n this.device = device;\n this.textarea = document.createElement(\"textarea\");\n this.textarea.classList.add('transcript');\n this.textarea.classList.add('transcript-style-2');\n this.textarea.style.display = 'none';\n parentElement.appendChild(this.textarea);\n /*\n this.vlist = new VirtualTextScroller(parentElement);\n this.vlist.create(parentElement, 1024, this.getMemoryLineAt.bind(this));\n this.vlist.maindiv.style.height = '8em';\n this.vlist.maindiv.style.overflow = 'clip';\n */\n }\n reset() {\n this.lastOutCount = 0;\n this.lastInCount = 0;\n this.textarea.style.display = 'none';\n }\n refresh() {\n var lastop = '';\n if (this.device.serialOut.length != this.lastOutCount) {\n var s = '';\n for (var ev of this.device.serialOut) {\n if (lastop != ev.op) {\n if (s != '') s += '\\n';\n if (ev.op === 'read') s += '<< ';\n else if (ev.op === 'write') s += '>> ';\n lastop = ev.op;\n }\n if (ev.value == 10) { s += '\\u21b5'; lastop = ''; }\n else { s += byteToASCII(ev.value); }\n }\n this.textarea.value = s;\n this.lastOutCount = this.device.serialOut.length;\n this.textarea.style.display = 'block';\n }\n }\n}\n"],
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"names": []
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}
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