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157 lines
3.9 KiB
Verilog
157 lines
3.9 KiB
Verilog
`ifndef SPRITE_RENDERER_H
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`define SPRITE_RENDERER_H
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`include "hvsync_generator.v"
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`include "sprite_bitmap.v"
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module sprite_renderer(clk, vstart, load, hstart, rom_addr, rom_bits,
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gfx, in_progress);
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input clk;
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input vstart; // start drawing (top border)
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input load; // ok to load sprite data?
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input hstart; // start drawing scanline (left border)
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output [3:0] rom_addr; // select ROM address
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input [7:0] rom_bits; // input bits from ROM
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output gfx; // output pixel
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output in_progress; // 0 if waiting for vstart
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assign in_progress = state != WAIT_FOR_VSTART;
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reg [2:0] state; // current state #
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reg [3:0] ycount; // number of scanlines drawn so far
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reg [3:0] xcount; // number of horiz. pixels in this line
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reg [7:0] outbits; // register to store bits from ROM
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// states
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localparam WAIT_FOR_VSTART = 0;
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localparam WAIT_FOR_LOAD = 1;
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localparam LOAD1_SETUP = 2;
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localparam LOAD1_FETCH = 3;
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localparam WAIT_FOR_HSTART = 4;
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localparam DRAW = 5;
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always @(posedge clk)
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begin
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case (state)
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WAIT_FOR_VSTART: begin
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ycount <= 0; // initialize vertical count
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gfx <= 0; // default pixel value (off)
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// wait for vstart, then next state
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if (vstart)
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state <= WAIT_FOR_LOAD;
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end
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WAIT_FOR_LOAD: begin
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xcount <= 0; // initialize horiz. count
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gfx <= 0;
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// wait for load, then next state
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if (load)
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state <= LOAD1_SETUP;
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end
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LOAD1_SETUP: begin
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rom_addr <= ycount; // load ROM address
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state <= LOAD1_FETCH;
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end
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LOAD1_FETCH: begin
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outbits <= rom_bits; // latch bits from ROM
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state <= WAIT_FOR_HSTART;
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end
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WAIT_FOR_HSTART: begin
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// wait for hstart, then start drawing
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if (hstart)
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state <= DRAW;
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end
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DRAW: begin
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// get pixel, mirroring graphics left/right
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gfx <= outbits[xcount<8 ? xcount[2:0] : ~xcount[2:0]];
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xcount <= xcount + 1;
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// finished drawing horizontal slice?
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if (xcount == 15) begin // pre-increment value
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ycount <= ycount + 1;
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// finished drawing sprite?
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if (ycount == 15) // pre-increment value
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state <= WAIT_FOR_VSTART; // done drawing sprite
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else
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state <= WAIT_FOR_LOAD; // done drawing this scanline
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end
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end
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// unknown state -- reset
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default: begin
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state <= WAIT_FOR_VSTART;
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end
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endcase
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end
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endmodule
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module sprite_render_test_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
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input clk;
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input hpaddle, vpaddle;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg [7:0] player_x;
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reg [7:0] player_y;
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reg [7:0] paddle_x;
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reg [7:0] paddle_y;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [3:0] car_sprite_addr;
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wire [7:0] car_sprite_bits;
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car_bitmap car(
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.yofs(car_sprite_addr),
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.bits(car_sprite_bits));
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wire vstart = {1'd0,player_y} == vpos;
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wire hstart = {1'd0,player_x} == hpos;
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wire car_gfx;
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wire in_progress;
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sprite_renderer renderer(
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.clk(clk),
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.vstart(vstart),
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.load(hsync),
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.hstart(hstart),
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.rom_addr(car_sprite_addr),
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.rom_bits(car_sprite_bits),
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.gfx(car_gfx),
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.in_progress(in_progress));
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always @(posedge hpaddle)
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paddle_x <= vpos[7:0];
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always @(posedge vpaddle)
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paddle_y <= vpos[7:0];
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always @(posedge vsync)
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begin
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player_x <= paddle_x;
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player_y <= paddle_y;
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end
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wire r = display_on && car_gfx;
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wire g = display_on && car_gfx;
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wire b = display_on && in_progress;
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assign rgb = {b,g,r};
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endmodule
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`endif
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