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24 lines
447 B
Verilog
24 lines
447 B
Verilog
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module LFSR(clk,reset,enable,lfsr);
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parameter NBITS = 8;
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parameter TAPS = 8'b11101;
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parameter INVERT = 0;
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input clk, reset;
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input enable;
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output reg [NBITS-1:0] lfsr;
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wire feedback = lfsr[NBITS-1] ^ INVERT;
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always @(posedge clk)
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begin
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if (reset) // initialize to 1
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lfsr <= {lfsr[NBITS-2:1], 1'b0, 1'b1};
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else if (enable)
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lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0);
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end
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endmodule;
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