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40 lines
817 B
Verilog
40 lines
817 B
Verilog
`include "hvsync_generator.v"
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`include "lfsr.v"
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module top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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wire [15:0] lfsr;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire star_enable = !hpos[8] & !vpos[8];
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// LFSR with period = 2^16-1 = 256*256-1
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LFSR #(16,16'b1000000001011,0) lfsr_gen(
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.clk(clk),
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.reset(reset),
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.enable(star_enable),
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.lfsr(lfsr));
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wire star_on = &lfsr[15:9];
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wire r = display_on && star_on && lfsr[0];
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wire g = display_on && star_on && lfsr[1];
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wire b = display_on && star_on && lfsr[2];
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assign rgb = {b,g,r};
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endmodule
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