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134 lines
2.8 KiB
Verilog
134 lines
2.8 KiB
Verilog
`include "hvsync_generator.v"
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`include "font_cp437_8x8.v"
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`include "ram.v"
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module tile_renderer(clk, reset, hpos, vpos, display_on,
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rgb,
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ram_addr, ram_read, ram_busy,
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rom_addr, rom_data);
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input clk, reset;
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input [8:0] hpos;
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input [8:0] vpos;
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input display_on;
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output [3:0] rgb;
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output reg [15:0] ram_addr;
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input [15:0] ram_read;
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output reg ram_busy;
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output [10:0] rom_addr;
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input [7:0] rom_data;
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reg [7:0] page_base = 8'h7e; // page table base (8 bits)
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reg [15:0] row_base; // row table base (16 bits)
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wire [4:0] row = vpos[7:3]; // 5-bit row, vpos / 8
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wire [4:0] col = hpos[7:3]; // 5-bit column, hpos / 8
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wire [2:0] yofs = vpos[2:0]; // scanline of cell (0-7)
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wire [2:0] xofs = hpos[2:0]; // which pixel to draw (0-7)
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reg [7:0] char;
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reg [7:0] attr;
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// tile ROM address
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assign rom_addr = {char, yofs};
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reg [15:0] row_buffer[0:31];
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// lookup char and attr
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always @(posedge clk) begin
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// time to read a row?
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if (vpos[2:0] == 7) begin
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// read row_base from page table (2 bytes)
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case (hpos[7:0])
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186: ram_busy <= 1;
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190: ram_addr <= {page_base, 3'b000, row};
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192: row_base <= ram_read;
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192+32: ram_busy <= 0;
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endcase
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// load row of tile data from RAM
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if (hpos >= 192 && hpos < 192+32) begin
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ram_addr <= row_base + 16'(hpos[4:0]);
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row_buffer[hpos[4:0]-2] <= ram_read;
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end
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end
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// latch character data
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if (hpos < 256) begin
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case (hpos[2:0])
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7: begin
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char <= row_buffer[col][7:0];
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attr <= row_buffer[col][15:8];
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end
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endcase
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end
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end
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// extract bit from ROM output
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assign rgb = display_on
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? (rom_data[~xofs] ? attr[3:0] : attr[7:4])
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: 0;
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endmodule
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module test_tilerender_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [3:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg [15:0] ram_addr;
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wire [15:0] ram_read;
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reg [15:0] ram_write = 0;
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reg ram_writeenable = 0;
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wire [10:0] rom_addr;
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wire [7:0] rom_data;
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wire ram_busy;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// RAM
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RAM_sync #(16,16) ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(ram_addr),
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.we(ram_writeenable)
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);
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tile_renderer tile_gen(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.display_on(display_on),
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.ram_addr(ram_addr),
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.ram_read(ram_read),
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.ram_busy(ram_busy),
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.rom_addr(rom_addr),
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.rom_data(rom_data),
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.rgb(rgb)
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);
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// tile ROM
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font_cp437_8x8 tile_rom(
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.addr(rom_addr),
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.data(rom_data)
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);
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endmodule
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