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27 lines
661 B
Verilog
27 lines
661 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam str = "string";
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function logic checkParameter(input logic [8:0] N);
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$display("x is %d.", N);
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if (N == 1)
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return 0;
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$fatal(1, "Parameter %d is invalid...%s and %s", N, str, "constant both work");
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endfunction
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`ifdef FAILING_ASSERTIONS
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localparam x = checkParameter(5);
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`else
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localparam x = checkParameter(1);
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`endif
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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