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104 lines
2.3 KiB
Verilog
104 lines
2.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg rst_n;
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// Take CRC data and apply to testblock inputs
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [2:0] pos1; // From test of Test.v
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wire [2:0] pos2; // From test of Test.v
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// End of automatics
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Test test (
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// Outputs
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.pos1 (pos1[2:0]),
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.pos2 (pos2[2:0]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.rst_n (rst_n));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {61'h0, pos1};
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// What checksum will we end up with
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`define EXPECTED_SUM 64'h039ea4d039c2e70b
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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rst_n <= ~1'b0;
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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rst_n <= ~1'b1;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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rst_n <= ~1'b1;
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end
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else if (cyc<90) begin
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if (pos1 !== pos2) $stop;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test
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#(parameter SAMPLE_WIDTH = 5 )
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(
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`ifdef verilator // Some simulators don't support clog2
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output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1,
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`else
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output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1,
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`endif
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output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2,
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// System
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input clk,
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input rst_n
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);
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function integer log2(input integer arg);
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begin
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for(log2=0; arg>0; log2=log2+1)
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arg = (arg >> 1);
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end
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endfunction
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always @ (posedge clk or negedge rst_n)
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if (!rst_n) begin
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pos1 <= 0;
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pos2 <= 0;
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end
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else begin
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pos1 <= pos1 + 1;
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pos2 <= pos2 + 1;
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end
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endmodule
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