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30 lines
603 B
Verilog
30 lines
603 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Mandy Xu.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off WIDTH
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//bug1088
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module t (/*AUTOARG*/
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// Outputs
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err_count,
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// Inputs
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clk, syndromes
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);
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input clk;
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input [7:0] syndromes;
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output reg [1:0] err_count = 0;
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localparam [95:0] M = 96'h4;
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wire [3:0] syn1 = syndromes[0+:M];
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always @(posedge clk) begin
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err_count <= {1'b0, |syn1};
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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