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50 lines
1018 B
Verilog
50 lines
1018 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg _ranit;
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reg [2:0] a;
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reg [33:0] wide;
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reg unused_r;
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initial _ranit = 0;
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always @ (posedge clk) begin : blockName
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begin // Verify begin/begin is legal
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unused_r <= 1'b1;
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end
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begin end // Verify empty is legal
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end
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wire one = 1'b1;
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wire [7:0] rand_bits = 8'b01xx_xx10;
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always @ (posedge clk) begin
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if (!_ranit) begin
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_ranit <= 1;
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//
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a = 3'b1xx;
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wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000;
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if (one !== 1'b1) $stop;
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if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// verilator lint_off UNUSED
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wire _unused_ok = |{1'b1, wide};
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// verilator lint_on UNUSED
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endmodule
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