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mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-11-05 11:06:28 +00:00
8bitworkshop/presets/verilog
2019-08-01 23:10:55 -04:00
..
.gitignore fixed multiplex issue in racing_game 2018-10-01 22:03:44 -04:00
7segment.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
ball_absolute.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
ball_paddle.v fixed ball_paddle.v 2018-10-09 19:37:38 -04:00
ball_slip_counter.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
binary_counter.v more verilog updates 2018-12-15 11:25:22 -05:00
chardisplay.v verilog: fixed RAM Text Display example incrementing by +2 2019-08-01 23:10:55 -04:00
clock_divider.v more verilog updates 2018-12-15 11:25:22 -05:00
cpu8.v verilog presets; early exit from jsasm errors 2018-09-08 19:14:51 -04:00
cpu16.v no more BOM on download files 2018-12-08 10:15:02 -05:00
cpu6502.v verilog: don't destroy() when module changes 2019-04-22 11:39:30 -04:00
cpu_platform.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
digits10.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
femto8.cfg make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
femto8.json make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
femto16.cfg make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
femto16.json make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
font_cp437_8x8.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
framebuf_vpu.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
framebuffer.v no more BOM on download files 2018-12-08 10:15:02 -05:00
gates.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
hvsync_generator.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
icestick.pcf fixed multiplex issue in racing_game 2018-10-01 22:03:44 -04:00
lfsr.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
Makefile fixed multiplex issue in racing_game 2018-10-01 22:03:44 -04:00
music.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
paddles.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
racing_game_cpu.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
racing_game.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
ram.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
scoreboard.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
sharedbuffer.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
skeleton.verilator make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
sound_generator.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
sprite_bitmap.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
sprite_renderer.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
sprite_rotation.v fixed unit tests 2018-10-03 15:06:48 -04:00
sprite_scanline_renderer.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
starfield.v minor scope tweaks, need phantomjs for wavedrom 2018-10-11 11:08:19 -04:00
switches.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
tank.v verilog tank example 2018-10-03 18:49:14 -04:00
test2.asm nes runToVsync; debug info changes 2018-08-03 12:18:08 -04:00
test_hvsync.v added comments to verilog examples 2018-10-01 12:30:47 -04:00
test.asm make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
tile_renderer.v verilog preset update 2018-12-13 18:25:54 -05:00