64 lines
1.5 KiB
Verilog
64 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Andrew Bardsley.
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// SPDX-License-Identifier: CC0-1.0
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// bug1071
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [3:0] array_1 [2:0];
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reg [3:0] array_2 [2:0];
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reg [3:0] array_3 [3:1];
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reg [3:0] elem;
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reg array_1_ne_array_2;
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reg array_1_eq_array_2;
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reg array_1_ne_array_3;
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reg array_1_eq_array_3;
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initial begin
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array_1[0] = 4'b1000;
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array_1[1] = 4'b1000;
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array_1[2] = 4'b1000;
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array_2[0] = 4'b1000;
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array_2[1] = 4'b1000;
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array_2[2] = 4'b1000;
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array_3[1] = 4'b1000;
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array_3[2] = 4'b0100;
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array_3[3] = 4'b0100;
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array_1_ne_array_2 = array_1 != array_2; // 0
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array_1_eq_array_2 = array_1 == array_2; // 0
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array_1_ne_array_3 = array_1 != array_3; // 1
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array_1_eq_array_3 = array_1 == array_3; // 1
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//Not legal: array_rxor = ^ array_1;
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//Not legal: array_rxnor = ^~ array_1;
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//Not legal: array_ror = | array_1;
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//Not legal: array_rand = & array_1;
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`ifdef TEST_VERBOSE
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$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
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$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
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`endif
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if (array_1_ne_array_2 !== 0) $stop;
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if (array_1_eq_array_2 !== 1) $stop;
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if (array_1_ne_array_3 !== 1) $stop;
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if (array_1_eq_array_3 !== 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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