164 lines
3.6 KiB
Verilog
164 lines
3.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifndef VERILATOR
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module t;
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg c0; // To t2 of t2.v
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reg c1; // To t2 of t2.v
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reg check; // To t2 of t2.v
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reg [1:0] clks; // To t2 of t2.v
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// End of automatics
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t2 t2 (/*AUTOINST*/
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// Inputs
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.clks (clks[1:0]),
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.c0 (c0),
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.c1 (c1),
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.check (check));
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task clockit (input v1, v0);
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c1 = v1;
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c0 = v0;
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clks[1] = v1;
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clks[0] = v0;
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`ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif
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#1;
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endtask
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initial begin
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check = '0;
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c0 = '0;
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c1 = '0;
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clks = '0;
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#1
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t2.clear();
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#10;
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for (int i=0; i<2; i++) begin
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clockit(0, 0);
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clockit(0, 0);
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clockit(0, 1);
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clockit(1, 1);
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clockit(0, 0);
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clockit(1, 1);
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clockit(1, 0);
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clockit(0, 0);
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clockit(1, 0);
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clockit(0, 1);
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clockit(0, 0);
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end
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check = 1;
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clockit(0, 0);
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end
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endmodule
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`endif
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`ifdef VERILATOR
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`define t2 t
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`else
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`define t2 t2
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`endif
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module `t2 (
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input [1:0] clks,
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input c0,
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input c1,
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input check
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);
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`ifdef T_CLK_2IN_VEC
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wire clk0 = clks[0];
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wire clk1 = clks[1];
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`else
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wire clk0 = c0;
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wire clk1 = c1;
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`endif
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integer p0 = 0;
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integer p1 = 0;
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integer p01 = 0;
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integer n0 = 0;
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integer n1 = 0;
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integer n01 = 0;
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integer vp = 0;
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integer vn = 0;
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integer vpn = 0;
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task clear;
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`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
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p0 = 0;
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p1 = 0;
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p01 = 0;
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n0 = 0;
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n1 = 0;
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n01 = 0;
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vp = 0;
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vn = 0;
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vpn = 0;
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endtask
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`define display_counts(text) begin \
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$write("[%0t] ",$time); \
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`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
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$write(text); \
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$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \
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end
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always @ (posedge clk0) begin
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p0 = p0 + 1; // Want blocking, so don't miss clock counts
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`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
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end
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always @ (posedge clk1) begin
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p1 = p1 + 1;
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`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
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end
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always @ (posedge clk0 or posedge clk1) begin
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p01 = p01 + 1;
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`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
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end
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always @ (negedge clk0) begin
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n0 = n0 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
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end
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always @ (negedge clk1) begin
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n1 = n1 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
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end
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always @ (negedge clk0 or negedge clk1) begin
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n01 = n01 + 1;
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`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
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end
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`ifndef VERILATOR
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always @ (posedge clks) begin
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vp = vp + 1;
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`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif
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end
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always @ (negedge clks) begin
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vn = vn + 1;
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`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif
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end
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always @ (posedge clks or negedge clks) begin
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vpn = vpn + 1;
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`ifdef TEST_VERBOSE `display_counts("or vec"); `endif
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end
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`endif
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always @ (posedge check) begin
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if (p0!=6) $stop;
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if (p1!=6) $stop;
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if (p01!=10) $stop;
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if (n0!=6) $stop;
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if (n1!=6) $stop;
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if (n01!=10) $stop;
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`ifndef VERILATOR
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if (vp!=6) $stop;
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if (vn!=6) $stop;
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if (vpn!=12) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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end
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endmodule
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