177 lines
3.7 KiB
Verilog
177 lines
3.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off GENCLK
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reg [7:0] cyc; initial cyc=0;
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reg [7:0] padd;
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reg dsp_ph1, dsp_ph2, dsp_reset;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] out; // From dspchip of t_dspchip.v
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// End of automatics
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t_dspchip dspchip (/*AUTOINST*/
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// Outputs
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.out (out[7:0]),
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// Inputs
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.dsp_ph1 (dsp_ph1),
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.dsp_ph2 (dsp_ph2),
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.dsp_reset (dsp_reset),
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.padd (padd[7:0]));
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always @ (posedge clk) begin
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$write("cyc %d\n",cyc);
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if (cyc == 8'd0) begin
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cyc <= 8'd1;
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dsp_reset <= 0; // Need a posedge
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padd <= 0;
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end
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else if (cyc == 8'd20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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cyc <= cyc + 8'd1;
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dsp_ph1 <= ((cyc&8'd3) == 8'd0);
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dsp_ph2 <= ((cyc&8'd3) == 8'd2);
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dsp_reset <= (cyc == 8'd1);
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padd <= cyc;
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//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
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case (cyc)
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default: $stop;
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8'd01: ;
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8'd02: ;
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8'd03: ;
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8'd04: ;
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8'd05: ;
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8'd06: ;
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8'd07: ;
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8'd08: ;
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8'd09: if (out!==8'h04) $stop;
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8'd10: if (out!==8'h04) $stop;
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8'd11: if (out!==8'h08) $stop;
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8'd12: if (out!==8'h08) $stop;
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8'd13: if (out!==8'h00) $stop;
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8'd14: if (out!==8'h00) $stop;
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8'd15: if (out!==8'h00) $stop;
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8'd16: if (out!==8'h00) $stop;
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8'd17: if (out!==8'h0c) $stop;
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8'd18: if (out!==8'h0c) $stop;
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8'd19: if (out!==8'h10) $stop;
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endcase
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end
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end
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endmodule
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module t_dspchip (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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dsp_ph1, dsp_ph2, dsp_reset, padd
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);
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input dsp_ph1, dsp_ph2, dsp_reset;
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input [7:0] padd;
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output [7:0] out;
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wire dsp_ph1, dsp_ph2;
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wire [7:0] out;
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wire pla_ph1, pla_ph2;
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wire out1_r;
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wire [7:0] out2_r, padd;
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wire clk_en;
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t_dspcore t_dspcore (/*AUTOINST*/
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// Outputs
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.out1_r (out1_r),
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.pla_ph1 (pla_ph1),
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.pla_ph2 (pla_ph2),
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// Inputs
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.dsp_ph1 (dsp_ph1),
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.dsp_ph2 (dsp_ph2),
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.dsp_reset (dsp_reset),
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.clk_en (clk_en));
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t_dsppla t_dsppla (/*AUTOINST*/
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// Outputs
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.out2_r (out2_r[7:0]),
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// Inputs
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.pla_ph1 (pla_ph1),
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.pla_ph2 (pla_ph2),
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.dsp_reset (dsp_reset),
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.padd (padd[7:0]));
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assign out = out1_r ? 8'h00 : out2_r;
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assign clk_en = 1'b1;
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endmodule
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module t_dspcore (/*AUTOARG*/
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// Outputs
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out1_r, pla_ph1, pla_ph2,
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// Inputs
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dsp_ph1, dsp_ph2, dsp_reset, clk_en
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);
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input dsp_ph1, dsp_ph2, dsp_reset;
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input clk_en;
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output out1_r, pla_ph1, pla_ph2;
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wire dsp_ph1, dsp_ph2, dsp_reset;
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wire pla_ph1, pla_ph2;
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reg out1_r;
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always @(posedge dsp_ph1 or posedge dsp_reset) begin
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if (dsp_reset)
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out1_r <= 1'h0;
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else
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out1_r <= ~out1_r;
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end
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assign pla_ph1 = dsp_ph1;
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assign pla_ph2 = dsp_ph2 & clk_en;
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endmodule
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module t_dsppla (/*AUTOARG*/
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// Outputs
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out2_r,
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// Inputs
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pla_ph1, pla_ph2, dsp_reset, padd
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);
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input pla_ph1, pla_ph2, dsp_reset;
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input [7:0] padd;
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output [7:0] out2_r;
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wire pla_ph1, pla_ph2, dsp_reset;
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wire [7:0] padd;
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reg [7:0] out2_r;
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reg [7:0] latched_r;
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always @(posedge pla_ph1 or posedge dsp_reset) begin
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if (dsp_reset)
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latched_r <= 8'h00;
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else
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latched_r <= padd;
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end
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always @(posedge pla_ph2 or posedge dsp_reset) begin
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if (dsp_reset)
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out2_r <= 8'h00;
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else
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out2_r <= latched_r;
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end
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endmodule
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