161 lines
3.3 KiB
Verilog
161 lines
3.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg reset;
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reg enable;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] out; // From test of Test.v
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// End of automatics
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[31:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.in (in[31:0]));
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wire [63:0] result = {32'h0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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reset <= (cyc < 5);
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enable <= cyc[4] || (cyc < 2);
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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`define EXPECTED_SUM 64'h01e1553da1dcf3af
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, reset, enable, in
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);
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input clk;
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input reset;
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input enable;
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input [31:0] in;
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output [31:0] out;
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// No gating
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reg [31:0] d10;
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always @(posedge clk) begin
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d10 <= in;
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end
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reg displayit;
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`ifdef VERILATOR // Harder test
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initial displayit = $c1("0"); // Something that won't optimize away
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`else
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initial displayit = '0;
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`endif
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// Obvious gating + PLI
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reg [31:0] d20;
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always @(posedge clk) begin
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if (enable) begin
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d20 <= d10; // Obvious gating
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if (displayit) begin
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$display("hello!"); // Must glob with other PLI statements
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end
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end
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end
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// Reset means second-level gating
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reg [31:0] d30, d31a, d31b, d32;
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always @(posedge clk) begin
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d32 <= d31b;
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if (reset) begin
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d30 <= 32'h0;
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d31a <= 32'h0;
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d31b <= 32'h0;
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d32 <= 32'h0; // Overlaps above, just to make things interesting
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end
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else begin
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// Mix two outputs
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d30 <= d20;
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if (enable) begin
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d31a <= d30;
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d31b <= d31a;
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end
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end
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end
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// Multiple ORs for gater
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reg [31:0] d40a,d40b;
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always @(posedge clk) begin
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if (reset) begin
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d40a <= 32'h0;
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d40b <= 32'h0;
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end
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if (enable) begin
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d40a <= d32;
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d40b <= d40a;
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end
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end
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// Non-optimizable
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reg [31:0] d91, d92;
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reg [31:0] inverted;
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always @(posedge clk) begin
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inverted = ~d40b;
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if (reset) begin
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d91 <= 32'h0;
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end
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else begin
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if (enable) begin
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d91 <= inverted;
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end
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else begin
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d92 <= inverted ^ 32'h12341234; // Inverted gating condition
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end
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end
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end
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wire [31:0] out = d91 ^ d92;
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endmodule
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