88 lines
2.4 KiB
Verilog
88 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_off GENCLK
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reg gendlyclk_r;
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reg [31:0] gendlydata_r;
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reg [31:0] dlydata_gr;
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reg genblkclk;
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reg [31:0] genblkdata;
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reg [31:0] blkdata_gr;
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wire [31:0] constwire = 32'h11;
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reg [31:0] initwire;
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integer i;
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initial begin
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for (i=0; i<10000; i=i+1) begin
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initwire = 32'h2200;
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end
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end
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wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
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wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
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always @ (posedge clk) begin
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gendlydata_r <= 32'h0011_0000;
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gendlyclk_r <= 0;
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// surefire lint_off SEQASS
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genblkclk = 0;
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genblkdata = 0;
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==2) begin
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gendlyclk_r <= 1;
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gendlydata_r <= 32'h00540000;
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genblkclk = 1;
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genblkdata = 32'hace;
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$write("[%0t] Send pulse\n", $time);
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end
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if (cyc==3) begin
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genblkdata = 32'hdce;
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gendlydata_r <= 32'h00ff0000;
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if (either != 32'h87542211) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// surefire lint_on SEQASS
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end
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always @ (posedge gendlyclk_r) begin
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if ($time>0) begin // Hack, don't split the block
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$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
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dlydata_gr <= 32'h80000000;
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// Delayed activity list will already be completed for gendlydata
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// because genclk is from a delayed assignment.
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// Thus we get the NEW not old value of gendlydata_r
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if (gendlydata_r != 32'h00540000) $stop;
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if (genblkdata != 32'hace) $stop;
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end
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end
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always @ (posedge genblkclk) begin
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if ($time>0) begin // Hack, don't split the block
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$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
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blkdata_gr <= 32'h07000000;
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// Clock from non-delayed assignment, we get old value of gendlydata_r
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`ifdef verilator `else // V3.2 races... technically legal
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if (gendlydata_r != 32'h00110000) $stop;
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`endif
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if (genblkdata != 32'hace) $stop;
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end
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end
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endmodule
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