125 lines
2.8 KiB
Verilog
125 lines
2.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [1:0] clkvec = crc[1:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [1:0] count; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.count (count[1:0]),
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// Inputs
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.clkvec (clkvec[1:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {62'h0, count};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`ifdef T_TEST1
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module Test
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(
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input wire [1:0] clkvec,
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// verilator lint_off MULTIDRIVEN
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output reg [1:0] count
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// verilator lint_on MULTIDRIVEN
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);
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genvar igen;
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generate
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for (igen=0; igen<2; igen=igen+1) begin : code_gen
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initial count[igen] = 1'b0;
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always @ (posedge clkvec[igen])
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count[igen] <= count[igen] + 1;
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end
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endgenerate
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always @ (count) begin
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$write("hi\n");
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end
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endmodule
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`endif
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`ifdef T_TEST2
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module Test
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(
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input wire [1:0] clkvec,
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// verilator lint_off MULTIDRIVEN
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output reg [1:0] count
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// verilator lint_on MULTIDRIVEN
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);
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genvar igen;
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generate
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for (igen=0; igen<2; igen=igen+1) begin : code_gen
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wire clk_tmp = clkvec[igen];
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// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
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// need to be.
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initial count[igen] = 1'b0;
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always @ (posedge clk_tmp)
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count[igen] <= count[igen] + 1;
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end
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endgenerate
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endmodule
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`endif
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`ifdef T_TEST3
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module Test
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(
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input wire [1:0] clkvec,
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output wire [1:0] count
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);
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genvar igen;
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generate
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for (igen=0; igen<2; igen=igen+1) begin : code_gen
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wire clk_tmp = clkvec[igen];
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reg tmp_count = 1'b0;
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always @ (posedge clk_tmp) begin
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tmp_count <= tmp_count + 1;
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end
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assign count[igen] = tmp_count;
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end
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endgenerate
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endmodule
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`endif
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