91 lines
1.9 KiB
Verilog
91 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [9:0] in = crc[9:0];
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/*AUTOWIRE*/
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.in (in[9:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {64'h0};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [9:0] in;
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reg a [9:0];
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integer ai;
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always @* begin
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for (ai=0;ai<10;ai=ai+1) begin
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a[ai]=in[ai];
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end
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end
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reg [1:0] b [9:0];
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integer j;
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generate
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genvar i;
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for (i=0; i<2; i=i+1) begin
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always @(posedge clk) begin
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for (j=0; j<10; j=j+1) begin
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if (a[j])
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b[i][j] <= 1'b0;
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else
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b[i][j] <= 1'b1;
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end
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end
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end
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endgenerate
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endmodule
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