34 lines
883 B
Verilog
34 lines
883 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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y, d2, m2, d3, m3
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);
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output [3:0] y;
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output [31:0] d2;
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output [31:0] m2;
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output [63:0] d3;
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output [63:0] m3;
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// bug775
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// verilator lint_off WIDTH
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assign y = ((0/0) ? 1 : 2) % 0;
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// bug2460
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reg [31:0] b;
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assign d2 = $signed(32'h80000000) / $signed(b);
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assign m2 = $signed(32'h80000000) % $signed(b);
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reg [63:0] b3;
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assign d3 = $signed(64'h80000000_00000000) / $signed(b3);
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assign m3 = $signed(64'h80000000_00000000) % $signed(b3);
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initial begin
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b = 32'hffffffff;
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b3 = 64'hffffffff_ffffffff;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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