147 lines
6.0 KiB
Verilog
147 lines
6.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off WIDTH
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//============================================================
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reg bad;
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initial begin
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bad=0;
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c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0);
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c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0);
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c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0);
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c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888);
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c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0);
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c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888);
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c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0);
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c96(96'h0003, 96'h0002, 96'h0001, 96'h0001);
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c96(96'h0003, 96'h0003, 96'h0001, 96'h0000);
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c96(96'h0003, 96'h0004, 96'h0000, 96'h0003);
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c96(96'h0000, 96'hffff, 96'h0000, 96'h0000);
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c96(96'hffff, 96'h0001, 96'hffff, 96'h0000);
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c96(96'hffff, 96'hffff, 96'h0001, 96'h0000);
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c96(96'hffff, 96'h0003, 96'h5555, 96'h0000);
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c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000);
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c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000);
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c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe);
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c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70);
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c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000);
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c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000);
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c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005);
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c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000);
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c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001);
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c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000);
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c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001);
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c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899);
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c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000);
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c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff);
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c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab);
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c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff);
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c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000);
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c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000);
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c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000);
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c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000);
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c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000);
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c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000);
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c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000);
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c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000);
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c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000);
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c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000);
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c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
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c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000);
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c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000);
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c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
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c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000);
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c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002);
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c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff);
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c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888);
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if (bad) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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task c96;
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input [95:0] u;
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input [95:0] v;
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input [95:0] expq;
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input [95:0] expr;
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c96u( u, v, expq, expr);
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c96s( u, v, expq, expr);
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c96s(-u, v,-expq,-expr);
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c96s( u,-v,-expq, expr);
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c96s(-u,-v, expq,-expr);
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endtask
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task c96u;
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input [95:0] u;
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input [95:0] v;
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input [95:0] expq;
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input [95:0] expr;
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reg [95:0] gotq;
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reg [95:0] gotr;
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gotq = u/v;
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gotr = u%v;
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if (gotq != expq && v!=0) begin
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bad = 1;
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end
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if (gotr != expr && v!=0) begin
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bad = 1;
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end
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if (bad
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`ifdef TEST_VERBOSE
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|| 1
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`endif
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) begin
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$write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
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// Test for v=0 to prevent Xs causing grief
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if (gotq != expq && v!=0) $write(" BADQ");
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if (gotr != expr && v!=0) $write(" BADR");
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$write("\n");
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end
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endtask
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task c96s;
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input signed [95:0] u;
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input signed [95:0] v;
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input signed [95:0] expq;
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input signed [95:0] expr;
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reg signed [95:0] gotq;
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reg signed [95:0] gotr;
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gotq = u/v;
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gotr = u%v;
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if (gotq != expq && v!=0) begin
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bad = 1;
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end
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if (gotr != expr && v!=0) begin
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bad = 1;
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end
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if (bad
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`ifdef TEST_VERBOSE
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|| 1
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`endif
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) begin
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$write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
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// Test for v=0 to prevent Xs causing grief
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if (gotq != expq && v!=0) $write(" BADQ");
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if (gotr != expr && v!=0) $write(" BADR");
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$write("\n");
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end
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endtask
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endmodule
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