55 lines
1.6 KiB
Verilog
55 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_order_a (/*AUTOARG*/
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// Outputs
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m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11,
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o_from_comandclk_levs12,
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// Inputs
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clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
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);
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input clk;
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input [7:0] a_to_clk_levm3;
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input [7:0] b_to_clk_levm1;
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input [7:0] c_com_levs10;
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input [7:0] d_to_clk_levm2;
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input [7:0] one;
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output [7:0] m_from_clk_lev1_r;
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output [7:0] n_from_clk_lev2;
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output [7:0] o_from_com_levs11;
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output [7:0] o_from_comandclk_levs12;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [7:0] m_from_clk_lev1_r;
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// End of automatics
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// surefire lint_off ASWEBB
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// surefire lint_off ASWEMB
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wire [7:0] a_to_clk_levm1;
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wire [7:0] a_to_clk_levm2;
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wire [7:0] c_com_levs11;
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reg [7:0] o_from_comandclk_levs12;
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wire [7:0] n_from_clk_lev2;
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wire [7:0] n_from_clk_lev3;
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assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
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assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
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always @ (posedge clk) begin
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m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
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end
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assign c_com_levs11 = c_com_levs10 + one;
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always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
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assign n_from_clk_lev2 = m_from_clk_lev1_r;
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assign n_from_clk_lev3 = n_from_clk_lev2;
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wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
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endmodule
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