20 lines
459 B
Verilog
20 lines
459 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_order_b (/*AUTOARG*/
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// Outputs
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o_subfrom_clk_lev2,
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// Inputs
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m_from_clk_lev1_r
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);
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input [7:0] m_from_clk_lev1_r;
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output [7:0] o_subfrom_clk_lev2;
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wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r;
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endmodule
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