71 lines
1.7 KiB
Verilog
71 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off BLKANDNBLK
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// verilator lint_off COMBDLY
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// verilator lint_off LATCH
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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// verilator lint_off MULTIDRIVEN
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reg [31:0] runnerm1, runner; initial runner = 0;
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reg [31:0] runcount; initial runcount = 0;
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reg [31:0] clkrun; initial clkrun = 0;
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reg [31:0] clkcount; initial clkcount = 0;
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always @ (/*AS*/runner) begin
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runnerm1 = runner - 32'd1;
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end
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reg run0;
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always @ (/*AS*/runnerm1) begin
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if ((runner & 32'hf)!=0) begin
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runcount = runcount + 1;
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runner = runnerm1;
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$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
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end
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run0 = (runner[8:4]!=0 && runner[3:0]==0);
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end
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always @ (posedge run0) begin
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// Do something that forces another combo run
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clkcount <= clkcount + 1;
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runner[8:4] <= runner[8:4] - 1;
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runner[3:0] <= 3;
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$write ("[%0t] posedge runner=%0x\n", $time, runner);
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end
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reg [7:0] cyc; initial cyc=0;
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always @ (posedge clk) begin
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$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
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cyc <= cyc + 8'd1;
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case (cyc)
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8'd00: begin
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runner <= 0;
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end
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8'd01: begin
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runner <= 32'h35;
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end
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default: ;
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endcase
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case (cyc)
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8'd02: begin
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if (runcount!=32'he) $stop;
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if (clkcount!=32'h3) $stop;
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end
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8'd03: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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end
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endmodule
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