102 lines
2.4 KiB
Verilog
102 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_off LATCH
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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// verilator lint_off MULTIDRIVEN
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// verilator lint_off BLKANDNBLK
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reg [31:0] comcnt;
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reg [31:0] dlycnt; initial dlycnt=0;
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reg [31:0] lastdlycnt; initial lastdlycnt = 0;
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reg [31:0] comrun; initial comrun = 0;
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reg [31:0] comrunm1;
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reg [31:0] dlyrun; initial dlyrun = 0;
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reg [31:0] dlyrunm1;
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always @ (posedge clk) begin
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$write("[%0t] cyc %d\n",$time,cyc);
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cyc <= cyc + 1;
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if (cyc==2) begin
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// Test # of iters
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lastdlycnt = 0;
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comcnt = 0;
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dlycnt <= 0;
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end
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if (cyc==3) begin
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dlyrun <= 5;
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dlycnt <= 0;
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end
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if (cyc==4) begin
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comrun = 4;
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end
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end
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always @ (negedge clk) begin
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if (cyc==5) begin
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$display("%d %d\n", dlycnt, comcnt);
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if (dlycnt != 32'd5) $stop;
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if (comcnt != 32'd19) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// This forms a "loop" where we keep going through the always till comrun=0
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reg runclk; initial runclk = 1'b0;
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always @ (/*AS*/comrunm1 or dlycnt) begin
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if (lastdlycnt != dlycnt) begin
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comrun = 3;
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$write ("[%0t] comrun=%0d start\n", $time, comrun);
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end
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else if (comrun > 0) begin
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comrun = comrunm1;
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if (comrunm1==1) begin
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runclk = 1;
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$write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
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end
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else $write ("[%0t] comrun=%0d\n", $time, comrun);
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end
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lastdlycnt = dlycnt;
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end
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always @ (/*AS*/comrun) begin
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if (comrun!=0) begin
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comrunm1 = comrun - 32'd1;
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comcnt = comcnt + 32'd1;
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$write("[%0t] comcnt=%0d\n",$time,comcnt);
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end
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end
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// This forms a "loop" where we keep going through the always till dlyrun=0
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reg runclkrst;
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always @ (posedge runclk) begin
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runclkrst <= 1;
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$write ("[%0t] runclk\n", $time);
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if (dlyrun > 0) begin
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dlyrun <= dlyrun - 32'd1;
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dlycnt <= dlycnt + 32'd1;
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$write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);
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end
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end
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always @* begin
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if (runclkrst) begin
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$write ("[%0t] runclk reset\n", $time);
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runclkrst = 0;
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runclk = 0;
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end
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end
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endmodule
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