64 lines
1.4 KiB
Verilog
64 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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fastclk
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);
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input fastclk;
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t_netlist tnetlist
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(.also_fastclk (fastclk),
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/*AUTOINST*/
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// Inputs
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.fastclk (fastclk));
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endmodule
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module t_netlist (/*AUTOARG*/
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// Inputs
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fastclk, also_fastclk
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);
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// surefire lint_off ASWEMB
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input fastclk;
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input also_fastclk;
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integer _mode; initial _mode = 0;
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// This entire module should optimize to nearly nothing...
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// verilator lint_off UNOPTFLAT
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reg [4:0] a,a2,b,c,d,e;
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// verilator lint_on UNOPTFLAT
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initial a=5'd1;
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always @ (posedge fastclk) begin
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b <= a+5'd1;
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c <= b+5'd1; // Better for ordering if this moves before previous statement
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end
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// verilator lint_off UNOPT
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always @ (d or /*AS*/a or c) begin
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e = d+5'd1;
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a2 = a+5'd1; // This can be pulled out of the middle of the always
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d = c+5'd1; // Better for ordering if this moves before previous statement
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end
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// verilator lint_on UNOPT
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always @ (posedge also_fastclk) begin
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if (_mode==5) begin
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if (a2 != 5'd2) $stop;
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if (e != 5'd5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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_mode <= _mode + 1;
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end
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endmodule
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