43 lines
912 B
Verilog
43 lines
912 B
Verilog
// DESCRIPTION: Verilator: Non-cutable edge in loop
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//
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// This code (stripped down from a much larger application) has a loop between
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// the use of ready in the first two always blocks. However it should
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// trivially trigger the $write on the first clk posedge.
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//
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// This is a regression test against issue 513.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg ready;
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initial begin
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ready = 1'b0;
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end
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always @(posedge ready) begin
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if ((ready === 1'b1)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge ready) begin
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if ((ready === 1'b0)) begin
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ready = 1'b1 ;
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end
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end
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always @(posedge clk) begin
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ready = 1'b1;
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end
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endmodule
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