63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [31:0] in_a;
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reg [31:0] in_b;
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reg [31:0] e,f,g,h;
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always @ (/*AS*/in_a) begin
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e = in_a;
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f = {e[15:0], e[31:16]};
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g = {f[15:0], f[31:16]};
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h = {g[15:0], g[31:16]};
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end
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// verilator lint_off UNOPTFLAT
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reg [31:0] e2,f2,g2,h2;
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always @ (/*AS*/f2) begin
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h2 = {g2[15:0], g2[31:16]};
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g2 = {f2[15:0], f2[31:16]};
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end
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always @ (/*AS*/in_a) begin
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f2 = {e2[15:0], e2[31:16]};
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e2 = in_a;
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end
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// verilator lint_on UNOPTFLAT
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d %x %x\n", cyc, h, h2);
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if (h != h2) $stop;
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if (cyc==1) begin
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in_a <= 32'h89a14fab;
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in_b <= 32'h7ab512fa;
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end
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if (cyc==2) begin
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in_a <= 32'hf4c11a42;
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in_b <= 32'h359967c6;
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if (h != 32'h4fab89a1) $stop;
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end
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if (cyc==3) begin
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if (h != 32'h1a42f4c1) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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