194 lines
4.5 KiB
Verilog
194 lines
4.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Ted Campbell.
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// SPDX-License-Identifier: CC0-1.0
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//With MULTI_CLK defined shows bug, without it is hidden
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`define MULTI_CLK
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//bug634
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module t (
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input i_clk_wr,
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input i_clk_rd
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);
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wire wr$wen;
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wire [7:0] wr$addr;
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wire [7:0] wr$wdata;
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wire [7:0] wr$rdata;
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wire rd$wen;
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wire [7:0] rd$addr;
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wire [7:0] rd$wdata;
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wire [7:0] rd$rdata;
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wire clk_wr;
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wire clk_rd;
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`ifdef MULTI_CLK
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assign clk_wr = i_clk_wr;
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assign clk_rd = i_clk_rd;
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`else
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assign clk_wr = i_clk_wr;
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assign clk_rd = i_clk_wr;
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`endif
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FooWr u_wr (
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.i_clk ( clk_wr ),
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.o_wen ( wr$wen ),
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.o_addr ( wr$addr ),
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.o_wdata ( wr$wdata ),
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.i_rdata ( wr$rdata )
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);
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FooRd u_rd (
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.i_clk ( clk_rd ),
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.o_wen ( rd$wen ),
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.o_addr ( rd$addr ),
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.o_wdata ( rd$wdata ),
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.i_rdata ( rd$rdata )
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);
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FooMem u_mem (
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.iv_clk ( {clk_wr, clk_rd } ),
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.iv_wen ( {wr$wen, rd$wen } ),
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.iv_addr ( {wr$addr, rd$addr } ),
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.iv_wdata ( {wr$wdata,rd$wdata} ),
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.ov_rdata ( {wr$rdata,rd$rdata} )
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);
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endmodule
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// Memory Writer
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module FooWr(
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input i_clk,
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output o_wen,
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output [7:0] o_addr,
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output [7:0] o_wdata,
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input [7:0] i_rdata
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);
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reg [7:0] cnt = 0;
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// Count [0,200]
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always @( posedge i_clk )
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if ( cnt < 8'd50 )
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cnt <= cnt + 8'd1;
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// Write addr in (10,30) if even
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assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
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assign o_addr = cnt;
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assign o_wdata = cnt;
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endmodule
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// Memory Reader
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module FooRd(
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input i_clk,
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output o_wen,
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output [7:0] o_addr,
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output [7:0] o_wdata,
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input [7:0] i_rdata
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);
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reg [7:0] cnt = 0;
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reg [7:0] addr_r;
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reg en_r;
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// Count [0,200]
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always @( posedge i_clk )
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if ( cnt < 8'd200 )
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cnt <= cnt + 8'd1;
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// Read data
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assign o_wen = 0;
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assign o_addr = cnt - 8'd100;
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// Track issued read
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always @( posedge i_clk )
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begin
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addr_r <= o_addr;
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en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
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end
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// Display to console 100 cycles after writer
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always @( negedge i_clk )
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if ( en_r ) begin
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`ifdef TEST_VERBOSE
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$display( "MEM[%x] == %x", addr_r, i_rdata );
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`endif
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if (addr_r != i_rdata) $stop;
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end
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endmodule
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// Multi-port memory abstraction
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module FooMem(
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input [2 -1:0] iv_clk,
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input [2 -1:0] iv_wen,
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input [2*8-1:0] iv_addr,
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input [2*8-1:0] iv_wdata,
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output [2*8-1:0] ov_rdata
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);
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FooMemImpl u_impl (
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.a_clk ( iv_clk [0*1+:1] ),
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.a_wen ( iv_wen [0*1+:1] ),
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.a_addr ( iv_addr [0*8+:8] ),
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.a_wdata ( iv_wdata[0*8+:8] ),
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.a_rdata ( ov_rdata[0*8+:8] ),
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.b_clk ( iv_clk [1*1+:1] ),
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.b_wen ( iv_wen [1*1+:1] ),
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.b_addr ( iv_addr [1*8+:8] ),
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.b_wdata ( iv_wdata[1*8+:8] ),
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.b_rdata ( ov_rdata[1*8+:8] )
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);
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endmodule
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// Dual-Port L1 Memory Implementation
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module FooMemImpl(
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input a_clk,
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input a_wen,
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input [7:0] a_addr,
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input [7:0] a_wdata,
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output reg [7:0] a_rdata,
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input b_clk,
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input b_wen,
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input [7:0] b_addr,
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input [7:0] b_wdata,
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output reg [7:0] b_rdata
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);
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/* verilator lint_off MULTIDRIVEN */
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reg [7:0] mem[0:255];
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/* verilator lint_on MULTIDRIVEN */
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always @( posedge a_clk )
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if ( a_wen )
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mem[a_addr] <= a_wdata;
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always @( posedge b_clk )
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if ( b_wen )
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mem[b_addr] <= b_wdata;
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always @( posedge a_clk )
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a_rdata <= mem[a_addr];
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always @( posedge b_clk )
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b_rdata <= mem[b_addr];
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endmodule
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