18 lines
506 B
Verilog
18 lines
506 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug 762
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module t(a0, y);
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input [3:0] a0;
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output [44:0] y;
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assign y[40] = 0;
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assign y[30] = 0;
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// verilator lint_off UNOPTFLAT
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assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
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endmodule
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