45 lines
783 B
Verilog
45 lines
783 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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tri z0;
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tri z1;
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updown #(0) updown0 (.z(z0));
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updown #(1) updown1 (.z(z1));
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always @ (posedge clk) begin
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if (z0 !== 0) $stop;
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if (z1 !== 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module updown #(parameter UP=0)
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(inout z);
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generate
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if (UP) begin
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t_up sub (.z);
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end
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else begin
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t_down sub (.z);
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end
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endgenerate
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endmodule
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module t_up (inout tri1 z);
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endmodule
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module t_down (inout tri0 z);
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endmodule
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