77 lines
1.5 KiB
Verilog
77 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [2:0] in;
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wire a,y,y_fixed;
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wire b = in[0];
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wire en = in[1];
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pullup(a);
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ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
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initial in=0;
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// Test loop
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always @ (posedge clk) begin
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in <= in + 1;
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$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
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if (en) begin
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// driving b
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// a should be b
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// y and yfix should also be b
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if (a!=b || y != b || y_fixed != b) begin
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$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
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$stop;
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end
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end else begin
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// not driving b
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// a should be 1 (pullup)
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// y and yfix shold be 1
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if (a!=1 || y != 1 || y_fixed != 1) begin
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$display( "Expected a,y,yfix == 1");
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$stop;
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end
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end
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if (in==3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module ChildA(inout A, input B, input en, output Y, output Yfix);
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// workaround
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wire a_in = A;
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ChildB childB(.A(A), .Y(Y));
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assign A = en ? B : 1'bz;
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ChildB childBfix(.A(a_in),.Y(Yfix));
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endmodule
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module ChildB(input A, output Y);
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assign Y = A;
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endmodule
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