29 lines
817 B
Verilog
29 lines
817 B
Verilog
// DESCRIPTION: Verilator: Test of selection with unsized Z.
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//
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// Test selecting Z when size is not explicit. Issue 510.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [1:0] b;
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wire [1:0] c;
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wire [0:0] d; // Explicit width due to issue 508
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wire [0:0] e;
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// This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It
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// does require the tri-state Z. Since we get the same effect if b is
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// dimensioned [0:0], this may be connected to issue 508.
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assign b[1:0] = clk ? 2'bx : 'bz;
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assign c[1:0] = clk ? 2'bz : 'bx;
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assign d = clk ? 1'bx : 'bz;
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assign e = clk ? 1'bz : 'bx;
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endmodule // t
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