126 lines
4.4 KiB
Verilog
126 lines
4.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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wire one = '1;
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wire z0 = 'z;
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wire z1 = 'z;
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wire z2 = 'z;
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wire z3 = 'z;
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wire tog = cyc[0];
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// verilator lint_off PINMISSING
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t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing
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t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn());
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t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0));
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t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
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t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
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t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect
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t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one));
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t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one));
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t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
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t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
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t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing
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t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn());
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t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1));
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t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
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t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect
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t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
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t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one));
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t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one));
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t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
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t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
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t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing
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t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn());
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t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2));
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t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
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t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
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t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
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t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one));
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t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one));
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t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
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t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
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t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing
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t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn());
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t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3));
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t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
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t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
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t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
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t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one));
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t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one));
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t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
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t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
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// verilator lint_on PINMISSING
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t_tri0
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(line, expval, tn);
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input integer line;
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input expval;
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input tn; // Illegal to be inout; spec requires net connection to any inout
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tri0 tn;
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wire clk = t.clk;
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always @(posedge clk) if (tn !== expval) begin
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$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
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end
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endmodule
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module t_tri1
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(line, expval, tn);
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input integer line;
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input expval;
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input tn;
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tri1 tn;
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wire clk = t.clk;
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always @(posedge clk) if (tn !== expval) begin
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$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
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end
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endmodule
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module t_tri2
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(line, expval, tn);
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input integer line;
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input expval;
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input tn;
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pulldown(tn);
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wire clk = t.clk;
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always @(posedge clk) if (tn !== expval) begin
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$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
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end
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endmodule
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module t_tri3
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(line, expval, tn);
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input integer line;
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input expval;
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input tn;
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pullup(tn);
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wire clk = t.clk;
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always @(negedge clk) if (tn !== expval) begin
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$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
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end
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endmodule
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