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33 lines
602 B
Verilog
33 lines
602 B
Verilog
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`include "hvsync_generator.v"
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/*
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A simple test pattern using the hvsync_generator module.
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*/
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module test_hvsync_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [9:0] hpos;
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wire [9:0] vpos;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire r = display_on && (((hpos&7)==0) || ((vpos&7)==0));
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wire g = display_on && vpos[4];
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wire b = display_on && hpos[4];
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assign rgb = {b,g,r};
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endmodule
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