123 lines
2.2 KiB
Verilog
123 lines
2.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg b;
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wire vconst1 = 1'b0;
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wire vconst2 = !(vconst1);
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wire vconst3 = !vconst2;
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wire vconst = vconst3;
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wire qa;
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wire qb;
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wire qc;
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wire qd;
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wire qe;
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ta ta (.b(b), .vconst(vconst), .q(qa));
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tb tb (.clk(clk), .vconst(vconst), .q(qb));
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tc tc (.b(b), .vconst(vconst), .q(qc));
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td td (.b(b), .vconst(vconst), .q(qd));
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te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("%b",{qa,qb,qc,qd,qe});
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`endif
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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b <= 1'b1;
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end
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if (cyc==2) begin
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if (qa!=1'b1) $stop;
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if (qb!=1'b0) $stop;
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if (qd!=1'b0) $stop;
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b <= 1'b0;
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end
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if (cyc==3) begin
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if (qa!=1'b0) $stop;
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if (qb!=1'b0) $stop;
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if (qd!=1'b0) $stop;
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if (qe!=1'b0) $stop;
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b <= 1'b1;
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end
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if (cyc==4) begin
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if (qa!=1'b1) $stop;
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if (qb!=1'b0) $stop;
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if (qd!=1'b0) $stop;
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if (qe!=1'b1) $stop;
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b <= 1'b0;
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end
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if (cyc==5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module ta (
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input vconst,
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input b,
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output reg q);
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always @ (/*AS*/b or vconst) begin
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q = vconst | b;
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end
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endmodule
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module tb (
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input vconst,
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input clk,
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output reg q);
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always @ (posedge clk) begin
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q <= vconst;
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end
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endmodule
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module tc (
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input vconst,
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input b,
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output reg q);
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always @ (posedge vconst) begin
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q <= b;
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$stop;
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end
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endmodule
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module td (
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input vconst,
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input b,
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output reg q);
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always @ (/*AS*/vconst) begin
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q = vconst;
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end
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endmodule
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module te (
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input clk,
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input vconst,
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input b,
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output reg q);
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reg qmid;
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always @ (posedge vconst or posedge clk) begin
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qmid <= b;
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end
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always @ (posedge clk or posedge vconst) begin
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q <= qmid;
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end
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endmodule
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