57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Test of gated clock detection
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//
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// The code as shown generates a result by a delayed assignment from PC. The
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// creation of the result is from a clock gated from the clock that sets
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// PC. Howevever since they are essentially the same clock, the result should
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// be delayed by one cycle.
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//
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// Standard Verilator treats them as different clocks, so the result stays in
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// step with the PC. An event drive simulator always allows the clock to win.
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//
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// The problem is caused by the extra loop added by Verilator to the
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// evaluation of all internally generated clocks (effectively removed by
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// marking the clock enable).
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//
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// This test is added to facilitate experiments with solutions.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Jeremy Bennett <jeremy.bennett@embecosm.com>.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg gated_clk_en = 1'b0 ;
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reg [1:0] pc = 2'b0;
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reg [1:0] res = 2'b0;
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wire gated_clk = gated_clk_en & clk;
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always @(posedge clk) begin
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pc <= pc + 1;
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gated_clk_en <= 1'b1;
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end
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always @(posedge gated_clk) begin
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res <= pc;
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end
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always @(posedge clk) begin
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if (pc == 2'b11) begin
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// Correct behaviour is that res should be lagging pc in the count
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// by one cycle
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if (res == 2'b10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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end
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endmodule
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