73 lines
1.3 KiB
Verilog
73 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test for generate IF constants
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//
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// The given generate loop should have a constant expression as argument. This
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// test checks it really does evaluate as constant.
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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`define MAX_SIZE 4
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Set the parameters, so that we use a size less than MAX_SIZE
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test_gen
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#(.SIZE (2),
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.MASK (4'b1111))
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i_test_gen (.clk (clk));
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// This is only a compilation test, but for good measure we do one clock
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// cycle.
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integer count;
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initial begin
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count = 0;
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end
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always @(posedge clk) begin
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if (count == 1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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count = count + 1;
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end
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end
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endmodule // t
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module test_gen
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#( parameter
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SIZE = `MAX_SIZE,
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MASK = `MAX_SIZE'b0)
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Generate blocks that rely on short-circuiting of the logic to avoid
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// errors.
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generate
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if ((SIZE < 8'h04) && MASK[0]) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write ("Generate IF MASK[0] = %d\n", MASK[0]);
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`endif
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end
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end
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endgenerate
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endmodule
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