174 lines
3.6 KiB
Verilog
174 lines
3.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [7:0] crc;
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genvar g;
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wire [7:0] out_p1;
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wire [15:0] out_p2;
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wire [7:0] out_p3;
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wire [7:0] out_p4;
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paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
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paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
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paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
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gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
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wire [7:0] out_ef;
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enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
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cyc <= cyc + 1;
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crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
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if (cyc==0) begin
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// Setup
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crc <= 8'hed;
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end
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else if (cyc==1) begin
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end
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else if (cyc==3) begin
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if (out_p1 !== 8'h2d) $stop;
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if (out_p2 !== 16'h2d2d) $stop;
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if (out_p3 !== 8'h78) $stop;
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if (out_p4 !== 8'h44) $stop;
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if (out_ef !== 8'hda) $stop;
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end
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else if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module gencase (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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parameter MODE = 0;
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input [7:0] in;
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output [7:0] out;
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generate // : genblk1
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begin
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case (MODE)
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2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
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default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
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endcase
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end
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endgenerate
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endmodule
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module paramed (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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parameter WIDTH = 1;
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parameter MODE = 0;
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input [WIDTH-1:0] in;
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output [WIDTH-1:0] out;
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generate
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if (MODE==0) initial $write("Mode=0\n");
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// No else
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endgenerate
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`ifndef NC // for(genvar) unsupported
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`ifndef ATSIM // for(genvar) unsupported
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generate
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// Empty loop body, local genvar
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for (genvar j=0; j<3; j=j+1) begin end
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// Ditto to make sure j has new scope
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for (genvar j=0; j<5; j=j+1) begin end
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endgenerate
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`endif
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`endif
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generate
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endgenerate
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genvar i;
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generate
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if (MODE==0) begin
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// Flip bitorder, direct assign method
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for (i=0; i<WIDTH; i=i+1) begin
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assign out[i] = in[WIDTH-i-1];
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end
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end
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else if (MODE==1) begin
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// Flip using instantiation
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for (i=0; i<WIDTH; i=i+1) begin
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integer from = WIDTH-i-1;
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if (i==0) begin // Test if's within a for
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mbuf m0 (.q(out[i]), .a(in[from]));
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end
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else begin
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mbuf ma (.q(out[i]), .a(in[from]));
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end
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end
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end
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else begin
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for (i=0; i<WIDTH; i=i+1) begin
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mbuf ma (.q(out[i]), .a(in[i^1]));
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end
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end
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endgenerate
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endmodule
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module mbuf (
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input a,
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output q
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);
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assign q = a;
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endmodule
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module enflop (clk, oe_e1, a,q);
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parameter WIDTH=1;
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input clk;
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input oe_e1;
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input [WIDTH-1:0] a;
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output [WIDTH-1:0] q;
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reg [WIDTH-1:0] oe_r;
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reg [WIDTH-1:0] q_r;
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
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enflop_one enflop_one
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(.clk (clk),
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.d (a[i]),
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.q_r (q_r[i]));
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always @(posedge clk) oe_r[i] <= oe_e1;
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assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
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end
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endgenerate
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endmodule
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module enflop_one (
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input clk,
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input d,
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output reg q_r
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);
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always @(posedge clk) q_r <= d;
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endmodule
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