49 lines
875 B
Verilog
49 lines
875 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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Testit testit (/*AUTOINST*/
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// Inputs
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.clk (clk));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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end
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else if (cyc<10) begin
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Testit (clk);
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input clk;
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genvar igen;
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generate
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for (igen=0; igen<0; igen=igen+1) begin : test_gen
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always @ (posedge clk) begin
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$display("igen1 = %d", igen);
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$stop;
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end
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end
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endgenerate
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endmodule
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