51 lines
1.1 KiB
Verilog
51 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// bug749
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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genvar g;
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for (g=1; g<3; ++g) begin : gblk
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sub2 #(.IN(g)) u ();
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//sub #(.IN(g)) u2 ();
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end
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sub1 #(.IN(0)) u ();
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always @ (posedge clk) begin
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if (t.u.IN != 0) $stop;
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if (t.u.FLAVOR != 1) $stop;
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//if (t.u2.IN != 0) $stop; // This should be not found
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if (t.gblk[1].u.IN != 1) $stop;
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if (t.gblk[2].u.IN != 2) $stop;
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if (t.gblk[1].u.FLAVOR != 2) $stop;
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if (t.gblk[2].u.FLAVOR != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub1 (/*AUTOARG*/);
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parameter [31:0] IN = 99;
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parameter FLAVOR = 1;
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`ifdef TEST_VERBOSE
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initial $display("%m");
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`endif
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endmodule
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module sub2 (/*AUTOARG*/);
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parameter [31:0] IN = 99;
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parameter FLAVOR = 2;
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`ifdef TEST_VERBOSE
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initial $display("%m");
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`endif
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endmodule
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