110 lines
5.4 KiB
Verilog
110 lines
5.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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genvar g;
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integer i;
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reg [31:0] v;
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reg [31:0] gen_pre_PLUSPLUS = 32'h0;
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reg [31:0] gen_pre_MINUSMINUS = 32'h0;
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reg [31:0] gen_post_PLUSPLUS = 32'h0;
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reg [31:0] gen_post_MINUSMINUS = 32'h0;
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reg [31:0] gen_PLUSEQ = 32'h0;
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reg [31:0] gen_MINUSEQ = 32'h0;
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reg [31:0] gen_TIMESEQ = 32'h0;
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reg [31:0] gen_DIVEQ = 32'h0;
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reg [31:0] gen_MODEQ = 32'h0;
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reg [31:0] gen_ANDEQ = 32'h0;
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reg [31:0] gen_OREQ = 32'h0;
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reg [31:0] gen_XOREQ = 32'h0;
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reg [31:0] gen_SLEFTEQ = 32'h0;
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reg [31:0] gen_SRIGHTEQ = 32'h0;
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reg [31:0] gen_SSRIGHTEQ = 32'h0;
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generate
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for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
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for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
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for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
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for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
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for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
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for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
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for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
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for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
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for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
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for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
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for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
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for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
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for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
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for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
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for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
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endgenerate
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 3) begin
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`ifdef TEST_VERBOSE
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$write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS);
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$write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS);
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$write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS);
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$write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS);
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$write("gen_PLUSEQ %b\n", gen_PLUSEQ);
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$write("gen_MINUSEQ %b\n", gen_MINUSEQ);
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$write("gen_TIMESEQ %b\n", gen_TIMESEQ);
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$write("gen_DIVEQ %b\n", gen_DIVEQ);
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$write("gen_MODEQ %b\n", gen_MODEQ);
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$write("gen_ANDEQ %b\n", gen_ANDEQ);
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$write("gen_OREQ %b\n", gen_OREQ);
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$write("gen_XOREQ %b\n", gen_XOREQ);
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$write("gen_SLEFTEQ %b\n", gen_SLEFTEQ);
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$write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ);
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$write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ);
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`endif
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if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
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if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop;
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if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
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if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
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if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
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if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
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if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
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if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
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if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
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if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop;
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if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop;
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if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop;
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if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
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if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
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if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
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v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
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v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
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v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
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v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
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v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
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v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
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v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop;
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v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
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v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
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v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
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v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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