37 lines
682 B
Verilog
37 lines
682 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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localparam N = 31;
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wire [31:0] vec;
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generate
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genvar g; // bug461
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begin : topgen
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for (g=0; g<N; ++g) begin : gfor
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assign vec[g] = (g<2);
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end
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end
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endgenerate
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 3) begin
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if (vec != 32'b0011) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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