50 lines
1.1 KiB
Verilog
50 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Alex Solomatnikov.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [6-1:0] foo[4-1:0];
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//initial $display("%m: %p\n", foo);
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//initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice
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//logic [6-1:0] foo2[4-1:0][5:6];
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//initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal
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dut #(.W(6),
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.D(4)) udut(.clk(clk),
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.foo(foo[4-1:0]));
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endmodule
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module dut
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#(parameter W = 1,
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parameter D = 1)
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(input logic clk,
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input logic [W-1:0] foo[D-1:0]);
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genvar i, j;
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generate
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for (j = 0; j < D; j++) begin
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for (i = 0; i < W; i++) begin
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suba ua(.clk(clk), .foo(foo[j][i]));
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end
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end
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endgenerate
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endmodule
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module suba
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(input logic clk,
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input logic foo);
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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