34 lines
585 B
Verilog
34 lines
585 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sub #(10,11,12,13) sub ();
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endmodule
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module sub ();
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parameter A = 0;
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parameter B = 1;
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ip ip();
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parameter C = 2;
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parameter D = 3;
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initial begin
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if (A!=10) $stop;
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if (B!=11) $stop;
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if (C!=12) $stop;
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if (D!=13) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module ip;
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endmodule
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