86 lines
1.9 KiB
Verilog
86 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Varun Koyyalagunta.
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// SPDX-License-Identifier: CC0-1.0
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// bug1015
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [1:0] i = crc[1:0];
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logic [1:0] o [13:10] ;
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Test test (/*AUTOINST*/
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// Outputs
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.o (o/*[1:0].[3:0]*/),
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// Inputs
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.i (i[1:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc<10) begin
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sum <= '0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hb42b2f48a0a9375a
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test
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(
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output logic [1:0] o [3:0],
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//but this works
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//logic [N-1:0] o
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input [1:0] i);
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parameter N = 4;
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logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3};
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sub sub [N-1:0] (.o (o), // many-to-many
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.a (a), // many-to-many
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.i (i)); // many-to-one
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endmodule
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module sub
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(
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input logic [1:0] i,
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input logic [1:0] a,
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output logic [1:0] o
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);
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assign o = i + a;
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endmodule
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