94 lines
1.9 KiB
Verilog
94 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by engr248.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] in = 0;
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wire [31:0] out;
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Test test(
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.out(out[31:0]),
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.clk(clk),
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.in (in[31:0])
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);
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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interface Intf ();
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endinterface
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module Select
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#(
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parameter int NUM_MASTER = 1
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)
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(
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Intf Upstream,
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Intf Downstream[NUM_MASTER]
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);
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endmodule
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module Crossbar
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#(
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parameter int NUM_MASTER = 1,
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parameter int NUM_SLAVE = 1
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)
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(
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Intf Masters[NUM_MASTER]
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);
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Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0]();
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genvar i;
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for (i = 0; i < NUM_MASTER; i = i + 1) begin
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Select #(
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.NUM_MASTER(NUM_SLAVE)
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)
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select_inst (
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.Upstream(Masters[i]),
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// Following line seems to trigger a bad calculation for dimension where port
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// is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE
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.Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)])
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// The following line works as intended and should be functionally identical to the above line
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// .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)])
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);
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end
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endmodule
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module Test
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(
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input clk,
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input [31:0] in,
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output reg [31:0] out
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);
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always @(posedge clk) begin
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out <= in;
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end
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Intf MST[10]();
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Crossbar #(
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.NUM_MASTER(10),
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.NUM_SLAVE(1)
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)
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xbar_inst (
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.Masters(MST)
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);
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endmodule
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