58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// bug1001
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interface intf
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#(parameter PARAM = 0)
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();
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logic val;
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endinterface
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module t();
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generate
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if (1) begin
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intf #(.PARAM(2)) my_intf ();
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assign my_intf.val = '1;
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end else begin
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intf #(.PARAM(3)) my_intf ();
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assign my_intf.val = '0;
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end
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endgenerate
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generate
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begin
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if (1) begin
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intf #(.PARAM(2)) my_intf ();
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assign my_intf.val = '1;
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end else begin
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intf #(.PARAM(3)) my_intf ();
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assign my_intf.val = '0;
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end
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end
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endgenerate
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generate
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begin
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begin
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if (1) begin
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intf #(.PARAM(2)) my_intf ();
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assign my_intf.val = '1;
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end else begin
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intf #(.PARAM(3)) my_intf ();
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assign my_intf.val = '0;
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end
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end
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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