25 lines
551 B
Verilog
25 lines
551 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Adrian Wise.
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// SPDX-License-Identifier: CC0-1.0
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//bug1246
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module t(input clk);
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my_interface iface();
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my_module m(.clk(clk), iface);
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endmodule
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module my_module(input clk, my_interface.my_port iface);
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always @(posedge clk) begin
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iface.b <= iface.a;
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iface.c <= iface.a;
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end
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endmodule
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interface my_interface;
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logic a, b, c;
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modport my_port(input a, output b, c);
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endinterface
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