57 lines
1.1 KiB
Verilog
57 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test of the +1364-1995ext+ and +systemverilogext+ flags.
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//
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// This source code contains constructs that are valid in SystemVerilog 2009
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// but not in Verilog 1995. So it should fail if we set the language to be
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// Verilog 1995, but not SystemVerilog 2009.
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//
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// Compile only test, so no need for "All Finished" output.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [1:0] res;
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// Instantiate the test
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test test_i (/*AUTOINST*/
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// Outputs
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.res (res),
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// Inputs
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.clk (clk),
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.in (1'b1));
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endmodule
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module test (// Outputs
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res,
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// Inputs
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clk,
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in
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);
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output [1:0] res;
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input clk;
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input in;
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// This is a SystemVerilog 2009 only test
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generate
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genvar i;
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for (i=0; i<2; i=i+1) begin
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always @(posedge clk) begin
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unique0 case (i)
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0: res[0:0] <= in;
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1: res[1:1] <= in;
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endcase
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end
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end
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endgenerate
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endmodule
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