23 lines
527 B
Verilog
23 lines
527 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test of the +verilog2001ext+ and +verilog2005ext+ flags.
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//
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// This source code uses the uwire declaration, which is only valid in Verilog
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// 2005.
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//
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// Compile only test, so no need for "All Finished" output.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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uwire w; // Only in Verilog 2005
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endmodule
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